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參數(shù)資料
| 型號： | AM79C940JCW |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁數(shù)： | 72/122頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940JCW |
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AMD
72
Am79C940
Receive Collision Count (RCVCC) (REG ADDR 27)
RCVCC [7–0]
The Receive Collision Count (RCVCC) is a read only
8-bit counter, incremented when the receiver detects a
collision on the network. Note that the RCVCC value re-
turned in the Receive Frame Status (RFS3) will freeze at
a value of 255, whereas this register based version of
RCVCC is free running. The value will roll over after 255
receive collisions have been detected, setting the
RCVCCO bit (in the Interrupt Register and asserting the
INTR
pin if the corresponding mask bit (RCVCCOM in
the Interrupt Mask Register ) is cleared. RCVCC will be
reset to zero when read.
User Test Register (UTR)
The User Test Register is used to put the chip into test
configurations. All bits within the Test Register are
cleared upon a hardware or software reset. Bit assign-
ments are as follows:
(REG ADDR 29)
RTRE
RTRD
RPA
FCOLL
RCVFCSE
LOOP [1–0]
RES
Bit
Name
Description
Bit 7
RTRE
Reserved Test Register Enable.
Access to the Reserved Test
Registers should not be at-
tempted by the user.
Note that
access to the Reserved Test
Register may cause damage to
the MACE device if configured
in a system board application.
Access to the Reserved Test
Register is prevented, regard-
less of the state of RTRE, once
RTRD has been set. RTRE is
cleared by activation of the
RE-
SET
pin or SWRST bit.
Reserved Test Register Disable.
When set, access to the Re-
served Test Registers is inhib-
ited, and further writes to the
RTRD bit are ignored. Access to
the Reserved Test Register is
prevented, regardless of the
state of RTRE, once RTRD has
been set. RTRD can only be
cleared by hardware or software
reset.
Runt Packet Accept. Allows re-
ceive packets which are less than
the legal minimum as specified
by IEEE 802.3/Ethernet, to be
passed to the host interface via
the Receive FIFO. The receive
packets must be at least 8 bytes
(after SFD) in length to be
accepted. RPA is cleared by acti-
vation of the
RESET
pin or
SWRST bit.
Bit 6
RTRD
Bit 5
RPA
Bit 4
FCOLL
Force Collision. Allows the colli-
sion logic to be tested. The
MACE device should be in an in-
ternal loopback test for the
FCOLL test. When FCOLL = 1, a
collision will be forced during the
next transmission attempt. This
will result in 16 total transmission
attempts (if DRTRY = 0) with the
Retry Error reported in the Trans-
mit
Frame
Status
FCOLL is cleared by the activa-
tion of the
RESET
pin or SWRST
bit.
Receive FCS Enable. Allows the
hardware associated with the
FCS generation to be allocated
to the transmitter or receiver dur-
ing loopback diagnostics. When
clear, the FCS will be generated
and appended to the transmit
message
(providing
DXMTFCS in the Transmit
Frame Control is clear), and re-
ceived after the loopback proc-
ess through the Receive FIFO.
When set, the hardware associ-
ated with the FCS generation is
allocated to the receiver. A trans-
mit packet will be assumed to
contain the FCS in the last four
bytes of the frame passed
through the Transmit FIFO. The
received frame will have the FCS
calculated on the data field and
compared with the last four bytes
contained in the received mes-
sage. An FCS error will be
flagged in the Received Status
(RFS1) if the received and calcu-
lated values do not match.
RCVFCSE is only valid when in
any one of the loopback modes
as defined by LOOP [0–1]. Note
that if the receive frame is ex-
pected to be recognized on the
basis of a multicast address
match, the FCS logic must be al-
located
to
(RCVFCSE = 1). RCVFCSE is
cleared by activation of the
RESET
pin or SWRST bit.
register.
Bit3
RCVFCSE
that
the
receiver
Bit 2–1 LOOP [1–0] Loopback Control. The loopback
functions allow the MACE device
to receive its own transmitted
frames. Three levels of loopback
are provided as shown in the fol-
lowing table. During loopback
operation a multicast address
can only be recognized if
RCVFCSE = 1. LOOP [0–1] are
cleared by activation of the
RESET
pin or SWRST bit.
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