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參數(shù)資料
| 型號： | AM79C940JCW |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁數(shù)： | 24/122頁 |
| 文件大小： | 914K |
| 代理商： | AM79C940JCW |
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AMD
24
Am79C940
EAM/R
External Address Match/Reject (Input)
The incoming frame will be received dependent on the
receive operational mode of the MACE device, and the
polarity of the
EAM/R
pin. The
EAM/R
pin function is
programmed by use of the M/
R
bit in the Receive Frame
Control register. If the bit is set, the pin is configured as
EAM
. If the bit is reset, the pin is configured as
EAR
.
EAM/R
can be asserted during packet reception to ac-
cept or reject packets based on an external address
comparison.
SRDCLK
Serial Receive Data Clock (Input/Output)
The Serial Receive Data (SRD) output is synchronous
to SRDCLK running at the 10MHz receive data clock fre-
quency. The pin is configured as an input, only when the
GPSI port is selected. Note that when the 10BASE-T
port is selected, transition on SRDCLK will only occur
during receive activity. When the AUI or DAI port is se-
lected, transition on SRDCLK will occur during both
transmit and receive activity.
SRD Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance
SRD Output
SRD Output
SRD Output
SRD Output
High Impedance
Note:
PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
SRDCLK Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance
SRDCLK Output
SRDCLK Output
SRDCLK Output
SRDCLK Input
High Impedance (Note 2)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
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