
ADV7188
User Sub Map
Address Register
Rev. 0 | Page 94 of 112
Bit
Bit Description
7 6 5 4 3 2 1 0 Comments
x
x
0
1
x
x
0
1
Notes
They
cannot
be cleared or
masked. Register 0x46 is used
for this purpose.
x
1
0
CCAPD data detected
Current SD Field is Odd Numbered
Current SD Field is Even Numbered
MPU_STIM_INT = 0
MPU_STIM_INT = 1
Closed captioning not detected in
the input video signal
Closed captioning data detected in
the video input signal
Gemstar data not detected in the
input video signal
Gemstar data detected in the input
video signal
SD signal has not changed Field
from ODD to Even or vice versa
SD signal has changed Field from
ODD to Even or vice versa
Not used
Not used
Manual interrupt not Set
Manual interrupt Set
Do not clear
Clears CCAPD_Q bit
Do not clear
Clears GEMD_Q bit
Do not Clear
Clears SD_FIELD_CHNGD_Q bit
Not used
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Masks CCAPD_Q bit
Unmasks CCAPD_Q bit
Masks GEMD_Q bit
Unmasks GEMD_Q bit
Masks CGMS_CHNGD_Q bit
Masks SD_FIELD_CHNGD_Q bit
Unmasks SD_FIELD_CHNGD_Q bit
Not used
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not established
SD vertical sync lock established
SD horizontal sync lock not
established
SD horizontal sync lock established
Not used
SECAM lock not established
SECAM lock established
Not used
Not used
Not used
No Change in SD signal standard
detected at the output
A Change in SD signal standard is
detected at the output
Reserved
EVEN_FIELD
Reserved
MPU_STIM_INTRQ
CCAPD_Q
1
0
GEMD_Q
1
Reserved
SD_FIELD_CHNGD_Q
0
x
x
1
Reserved
Reserved
MPU_STIM_INTRQ_Q
0
1
0
1
0
1
x
x
x
0
0
1
0
1
0 0
0 0
0
0
1
0
1
0x46
Interrupt Status 2
(Read Only)
These bits can be cleared or
masked by registers 0x47 and
0x48, respectively.
Note that interrupt in register
0x46 for the CCAP, Gemstar,
CGMS and WSS data is using
the Mode 1 data slicer.
x
CCAPD_CLR
GEMD_CLR
Reserved
SD_FIELD_CHNGD_CLR
0
1
0
1
Reserved
Reserved
MPU_STIM_INTRQ_CLR
0x47
Interrupt Clear 2
(Write Only)
Note that interrupt in register
0x46 for the CCAP, Gemstar,
CGMS and WSS data is using
the Mode 1 data slicer.
0
CCAPD_MSKB
GEMD_MSKB
Reserved
SD_FIELD_CHNGD_MSKB
0
1
0
1
Reserved
Reserved
MPU_STIM_INTRQ_MSKB
0x48
Interrupt Mask 2
(Read/Write)
Note that interrupt in register
0x46 for the CCAP, Gemstar,
CGMS and WSS data is using
the Mode 1 data slicer.
SD_OP_50Hz. SD 60/50Hz frame rate at
output
SD_V_LOCK
SD_H_LOCK
x
x
x
0
1
x
1
0
Reserved
SCM_LOCK
Reserved
Reserved
Reserved
SD_OP_CHNG_Q. SD 60/50 Hz frame rate
at output
0x49
Raw Status 3
(Read Only)
These bits are status bits only.
They
cannot
be cleared or
masked. Register 0x4A is used
for this purpose.
0x4A
Interrupt Status 3
(Read Only)
1
These bits can be cleared and
masked by Registers 0x4B and
0x4C, respectively.