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參數(shù)資料
| 型號： | ADV7188 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| 中文描述： | 標清多格式視頻解碼器支持快速開關(guān)重疊 |
| 文件頁數(shù)： | 41/112頁 |
| 文件大小： | 943K |
| 代理商： | ADV7188 |
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ADV7188
The chroma can be delayed/advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where one can
no longer delay by luma pixel steps.
Rev. 0 | Page 41 of 112
For manual programming, use the following defaults:
CVBS input CTA[2:0] = 011
YC input CTA[2:0] = 101
YPrPb input CTA[2:0] =110
Table 60. CTA Function
CTA[2:0]
000
001
010
011 (default)
100
101
110
111
Description
Not used.
Chroma + 2 chroma pixel (early).
Chroma + 1 chroma pixel (early).
No delay.
Chroma – 1 chroma pixel (late).
Chroma – 2 chroma pixel (late).
Chroma – 3 chroma pixel (late).
Not used.
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
The HS begin and HS end registers allow the user to freely
position the HS output (pin) within the video line. The values
in HSB[10:0] and HSE[10:0] are measured in pixel units from
the falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
HSB[10:0] HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF, 00, 00, XY (see Figure 26). HSB[10:0] is set
to 00000000010, which is 2 LLC1 clock cycles from count[0].
The default value of HSB[10:0] is 0x002, indicating that the HS
pulse starts two pixels after the falling edge of HS.
.
Table 61. HS Timing Parameters (see Figure 26)
Characteristic
HS to Active Video
(LLC1 Clock Cycles)
(C in Figure 26) (default)
272
276
Standard
NTSC
NTSC Square
Pixel
PAL
HS Begin Adjust
(HSB[10:0]) (default)
00000000010
00000000010
HS End Adjust
(HSE[10:0]) (default)
00000000000
00000000000
Active Video
Samples/Line
(D in)
720Y + 720C = 1440
640Y + 640C = 1280
Total LLC1
Clock Cycles
(E in)
1716
1560
00000000010
00000000000
284
720Y + 720C = 1440
1728
0
E
VIDEO
LLC1
PBUS
HS
Cr
Y
FF
00
00
XY
80
10
80
10
80
10
FF
00
00
XY
Cb
Y
Cr
Y
Cb
Y
Cr
4 LLC1
D
HSB[10:0]
HSE[10:0]
C
E
D
SAV
ACTIVE VIDEO
H BLANK
EAV
Figure 26. HS Timing
HSE[10:0] HS End, Address 0x34 [2:0], Address 0x36 [7:0]
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF, 00, 00, XY (see Figure 26). HSE is set to
00000000000, which is 0 LLC1 clock cycles from count[0].
The default value of HSE[10:0] is 000, indicating that the HS
pulse ends 0 pixels after falling edge of HS.
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| ADV7189B | Multiformat SDTV Video Decoder |
| ADV7189BBSTZ268H | Multiformat SDTV Video Decoder |
| ADV7189BKSTZ10F | Multiformat SDTV Video Decoder |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7188BSTZ | 功能描述:IC DECODER VID MULTIFORM 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ | 功能描述:IC VIDEO DECODER SDTV 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189BBSTZ268H | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
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