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| 型號： | ADV7188 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| 中文描述： | 標清多格式視頻解碼器支持快速開關(guān)重疊 |
| 文件頁數(shù)： | 61/112頁 |
| 文件大?。?/td> | 943K |
| 代理商： | ADV7188 |
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ADV7188
Table 77. VITC Readback Registers
1
Signal Name
VITC_DATA_0[7:0]
VITC_DATA_1[7:0]
VITC_DATA_2[7:0]
VITC_DATA_3[7:0]
VITC_DATA_4[7:0]
VITC_DATA_5[7:0]
VITC_DATA_6[7:0]
VITC_DATA_7[7:0]
VITC_DATA_8[7:0]
VITC_CALC_CRC[7:0]
Rev. 0 | Page 61 of 112
Register Location
VDP_VITC_DATA_0[7:0] (VITC bits [9:2]
VDP_VITC_DATA_1[7:0] (VITC bits [19:12]
VDP_VITC_DATA_2[7:0] (VITC bits [29:22]
VDP_VITC_DATA_3[7:0] (VITC bits [39:32]
VDP_VITC_DATA_4[7:0] (VITC bits [49:42]
VDP_VITC_DATA_5[7:0] (VITC bits [59:52]
VDP_VITC_DATA_6[7:0] (VITC bits [69:62]
VDP_VITC_DATA_7[7:0] (VITC bits [79:72]
VDP_VITC_DATA_8[7:0] (VITC bits [89:82]
VDP_VITC_CALC_CRC[7:0]
Address (User Sub Map)
146
147
148
149
150
151
152
153
154
155
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
1
The register is a readback register; default value does not apply.
VPS/PDC/UTC/GEMSTAR
The readback registers for VPS, PDC and UTC have been
shared. Gemstar is a high data rate standard and so is available
only through the ancillary stream; however, for evaluation
purposes, any one line of Gemstar is available through I
2
C
registers sharing the same register space as PDC, UTC and VPS.
Thus only one standard out of VPS, PDC, UTC and Gemstar
can be read through the I
2
C at a time.
To identify the data that should be made available in the I
2
C
registers, the user has to program I2C_GS_VPS_PDC_UTC[1:0]
(register address 0x9C, User Sub Map).
I2C_GS_VPS_PDC_UTC (VDP) [1:0] Address 0x9C [6:5],
User Sub Map
Specifies which standard result to be available for I
2
C readback.
Table 78. I2C_GS_VPS_PDC_UTC[1:0] Function
I2C_GS_VPS_PDC_UTC
[1:0]
00 (default)
01
10
11
GS_PDC_VPS_UTC_CLEAR GS/PDC/VPS/UTC Clear,
Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
1—Re-initializes the GS/PDC/VPS/UTC data readback
registers.
Description
Gemstar 1x/2x.
VPS.
PDC.
UTC.
GS_PDC_VPS_UTC_AVL GS/PDC/VPS/UTC Available,
Address 0x78 [4], User Sub Map, Read Only
0—One of GS, PDC, VPS or UTC data was not detected.
1—One of GS, PDC, VPS, or UTC data was detected.
VDP_GS_VPS_PDC_UTC Readback Registers
See Table 79.
VPS
The VPS data bits are bi-phase decoded by the VDP. The
decoded data is available in both the ancillary stream and in the
I
2
C readback registers. VPS decoded data is available in the
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (addresses 0x84 – 0x90, User Sub Map). The GS_VPS_
PDC_UTC_AVL bit is set if the user had programmed
I2C_GS_VPS_PDC_UTC to 01, as explained in Table 78.
GEMSTAR
The Gemstar decoded data is made available in the ancillary
stream and any one line of Gemstar is also available in I
2
C
registers for evaluation purposes. To obtain Gemstar results in
I
2
C registers, the user has to program I2C_GS_VPS_
PDC_UTC to 00, as explained in Table 78.
VDP supports auto detection of Gemstar standard between
Gemstar 1× or Gemstar 2× and decodes accordingly. For this
auto detection mode to work the user has to set
AUTO_DETECT_GS_TYPE I
2
C bit (register 0x61 User Sub
Map) and program the decoder to decode Gemstar 2× on the
required lines through line programming. The type of Gemstar
decoded can be determined by observing the bit
GS_DATA_TYPE bit (Register 0x78, User Sub Map).
AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map
0 (default)—Disables autodetection of Gemstar type.
1—Enables autodetection.
GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only
Identifies the decoded Gemstar data type.
0—Gemstar 1× mode is detected. Read 2 data bytes from 0x84.
1—Gemstar 2× mode is detected. Read 4 data bytes from 0x84.
The Gemstar data that is available in the I
2
C register could be
from any line of the input video on which Gemstar was
decoded. To read the Gemstar data on a particular video line,
the user should use the Manual Configuration as described in
Table 65 and Table 66 and enable Gemstar decoding on the
required line only.
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| ADV7188BSTZ | 功能描述:IC DECODER VID MULTIFORM 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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