
ADV7188
For example
Rev. 0 | Page 42 of 112
1.
To shift the HS toward active video by 20 LLC1s, add 20
LLC1s to both HSB and HSE, that is HSB[10:0] =
[00000010110], HSE[10:0] = [00000010100]
2.
To shift the HS away from active video by 20 LLC1s, add 1696
LLC1s to both HSB and HSE (for NTSC), that is, HSB[10:0] =
[11010100010], HSE[10:0] = [11010100000]. 1696 is derived
from the NTSC total number of pixels = 1716.
To move 20 LLC1s away from active video is equal to subtracting
20 from 1716 and adding the result in binary to both HSB[10:0]
and HSE[10:0].
PHS Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit.
0 (default)—HS is active high.
1—HS is active low.
VS and FIELD Configuration
The following controls allow the user to configure the behavior
of the VS and FIELD output pins, and to generate embedded AV
codes:
ADV encoder-compatible signals via NEWAVMODE
PVS, PF
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
For NTSC control:
o
NVBEGDELO, NVBEGDELE, NVBEGSIGN,
NVBEG[4:0]
o
NVENDDELO, NVENDDELE, NVENDSIGN,
NVEND[4:0]
o
NFTOGDELO, NFTOGDELE, NFTOGSIGN,
NFTOG[4:0]
For PAL control:
o
PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0]
o
PVENDDELO, PVENDDELE, PVENDSIGN,
PVEND[4:0]
o
PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]
NEWAVMODE New AV Mode, Address 0x31 [4]
0—EAV/SAV codes are generated to suit ADI encoders. No
adjustments are possible.
1 (default)—Enables the manual position of the VSYNC, Field,
and AV codes using Register 0x34 to Register 0x37 and Register
0xE5 to Register 0xEA. Default register settings are CCIR656
compliant; see Figure 27 for NTSC and Figure 32 for PAL. For
recommended manual user settings, see Table 62 and Figure 28
for NTSC; see Table 63 and Figure 33 for PAL.
HVSTIM Horizontal VS Timing, Address 0x31 [3]
The HVSTIM bit allows the user to select where the VS signal is
being asserted within a line of video. Some interface circuitry
may require VS to go low while HS is low.
0 (default)—The start of the line is relative to HSE.
1—The start of the line is relative to HSB.
VSBHO VS Begin Horizontal Position Odd, Address 0x32 [7]
This bit selects the position within a line at which the VS pin
(not the bit in the AV code) becomes active. Some follow-on
chips require the VS pin to change state only when HS is
high/low.
0 (default)—The VS pin goes high at the middle of a line of
video (odd field).
1—The VS pin changes state at the start of a line (odd field).
VSBHE VS Begin Horizontal Position Even, Address 0x32 [6]
This bit selects the position within a line at which the VS pin
(not the bit in the AV code) becomes active. Some follow-on
chips require the VS pin to change state only when HS is
high/low.
0—The VS pin goes high at the middle of a line of video (even
field).
1 (default)—The VS pin changes state at the start of a line (even
field).
VSEHO VS End Horizontal Position Odd, Address 0x33 [7]
This bit selects the position within a line at which the VS pin
(not the bit in the AV code) becomes inactive. Some follow-on
chips require the VS pin to change state only when HS is
high/low.
0—The VS pin goes low (inactive) at the middle of a line of
video (odd field).
1 (default)—The VS pin changes state at the start of a line (odd
field).