
ADV7188
SETADC_SW_MAN_EN, Manual Input Muxing Enable,
Address C4 [7]
ADC0_sw[3:0], ADC0 Mux Configuration, Address 0xC3 [3:0]
ADC1_sw[3:0], ADC1 Mux Configuration, Address 0xC3 [7:4]
ADC2_sw[3:0], ADC2 Mux Configuration, Address 0xC4 [3:0]
ADC3_sw[3:0], ADC3 Mux Configuration, Address 0xF3 [7:4]
See Table 11.
Rev. 0 | Page 15 of 112
XTAL CLOCK INPUT PIN FUNCTIONALITY
XTAL_TTL_SEL, Address 0x13 [2]
The XTAL pad is normally part of the crystal oscillator circuit,
powered from a 1.8 V supply. For optimal clock generation, the
slice level of the input buffer of this circuit is at approximately
half the supply voltage. This makes it incompatible with TLL
level signals.
0 (default)—A crystal is used to generate the ADV7188’s clock.
1—An external TTL level clock is supplied. A different input
buffer can be selected, which slices at TTL-compatible levels.
This inhibits operation of the crystal oscillator and, therefore,
can only be used when a clock signal is applied.
28.63636 MHZ CRYSTAL OPERATION
EN28XTAL, Address 0x1D [6]
The ADV7188 can operate on two different base crystal
frequencies. Selecting one over the other can be desirable in
systems in which board crosstalk between different components
leads to undesirable interference between video signals. It is
recommended by ADI to use an XTAL of frequency 28.63636 MHz
to clock the ADV7188. The programming examples at the end
of this datasheet presume 28.63636 MHz crystal is used.
0 (default)—XTAL frequency is 27 MHz.
1—XTAL frequency is 28.63636 MHz.
ANTIALIASING FILTERS
The ADV7188 has optional antialiasing filters on each of the
four input channels. The filters are designed for SD video with
approximately 6 MHz bandwidth.
A plot of the filter response is shown in Figure 8. The filters
can be individually enabled via I
2
C under the control of
AA_FILT_EN[3:0].
AA_FILT_EN[0], Address 0xF3 [0]
0 (default)—The filter on channel 0 is disabled
1—The filter on channel 0 is enabled
AA_FILT_EN[1], Address 0xF3 [1]
0 (default)—The filter on channel 1 is disabled
1—The filter on channel 1 is enabled
AA_FILT_EN[2], Address 0xF3 [2]
0 (default)—The filter on channel 2 is disabled
1—The filter on channel 2 is enabled
AA_FILT_EN[3], Address 0xF3 [3]
0 (default)—The filter on channel 3 is disabled
1—The filter on channel 3 is enabled
1M
1G
0
FREQUENCY (Hz)
A
0
–2
–4
–6
–8
–10
10M
100M
RESPONSE OF AA FILTER WITH CALIBRATED CAPACITORS
Figure 8. Frequency Response of Internal ADV7188 Antialiasing Filters
SCART AND FAST BLANKING
The ADV7188 can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART
compatibility and overlay functionality.
This function is available when INSEL[3:0] is set appropriately
(see Table 9). Timing extraction is always performed by the
ADV7188 on the CVBS signal. However, a combination of the
CVBS and RGB inputs can be mixed and output under control
of I
2
C registers and the fast blank (FB) pin.
Four basic modes are supported:
Static Switch Mode
The FB pin is not used. The timing is extracted from the CVBS
signal, and either the CVBS content or RGB content can be
output under the control of CVBS_RGB_SEL. This mode allows
the selection of a full-screen picture from either source. Overlay
is not possible in static switch mode.
Fixed Alpha Blending
The FB pin is not used. The timing is extracted from the CVBS
signal, and an alpha blended combination of the video from the
CVBS and RGB sources is output. This alpha blending is
applied to the full screen. The alpha blend factor is selected with
the I
2
C signal MAN_ALPHA[6:0]
.
Overlay is not possible in
fixed alpha blending mode.