
ADV7188
Table 15. Fast Blank and Contrast Reduction Programmable Threshold I
2
C Controls
CNTR_ENABLE
FB_LEVEL[1:0]
0
00 (default)
0
01
0
10
0
11
1
00 (default)
1
01
1
10
1
11
Table 16. FB_STATUS Functions
FB_STATUS [3:0]
Bit Name
0
FB_STATUS.0
Rev. 0 | Page 18 of 112
CNTR_LEVEL[1:0]
XX
XX
XX
XX
00
01
10
11
Fast Blanking Threshold
1.4 V
1.6 V
1.8 V
2.0 V
1.6 V
1.8 V
2.0 V
2.2 V
Contrast Reduction Threshold
n/a
n/a
n/a
n/a
0.4 V
0.6 V
0.8 V
2.0 V
Description
FB_rise.
A high value indicates there has been a rising edge on FB since the last I
2
C
read. Value is cleared by current I
2
C read – self-clearing bit.
FB_fall.
A high value indicates there has been a falling edge on FB since the last I
2
C
read. Value is cleared by current I
2
C read – self-clearing bit.
FB_stat.
Value of FB input pin at time of read.
FB_high.
A high value indicates there has been a rising edge on FB since the last I
2
C
read. Value is cleared by current I
2
C read – self-clearing bit.
1
FB_STATUS.1
2
3
FB_STATUS.2
FB_STATUS.3
FB_INV, Address 0xED [3] (write only)
The interpretation of the polarity of the signal applied to the FB
pin can be changed using FB_INV.
0 (default)—The fast blank pin is active high.
1—The fast blank pin is active low.
READBACK OF FB PIN STATUS
FB_STATUS[3:0], Address 0xED [7:4]
FB_STATUS[3:0] is a readback value that provides the system
information on the status of the FB pins as shown in Table 16.
FB Timing
FB_SP_ADJUST[3:0], Address 0xEF [7:4]
The critical information extracted from the FB signal is the time
at which it switches relative to the input video. Due to small
timing inequalities either on the IC or on the PCB, it may be
necessary to adjust the result by fractions of one clock cycle.
This is controlled by FB_SP_ADJUST[3:0].
Each LSB of FB_SP_ADJUST[3:0] corresponds to 1/8 of an ADC
clock cycle. Increasing the value is equivalent to adding delay to
the FB signal. The reset value is chosen to give equalized channels
when the ADV7188 internal anti-aliasing filters are enabled and
there is no unintentional delay on the PCB.
The default value of FB_SP_ADJUST[3:0] is 0100.
Alignment of FB Signal
FB_DELAY[3:0], Address 0xF0 [3:0]
In the event of misalignment between the FB input signal and
the other input signals (CVBS, RGB) or unequalized delays in
their processing, it is possible to alter the delay of the FB signal
in 28.63636 MHz clock cycles. (For a finer granularity delay of
the FB signal, refer to FB_SP_ADJUST[3:0], Address 0xEF [7:4]
above.)
The default value of FB_DELAY[3:0] is 0100.
Color Space Converter Manual Adjust
FB_CSC_MAN, Address 0xEE [7]
As shown in Figure 9, the data from the CVBS source and the
RGB source are both converted to YPbPr before being combined.
For the RGB source, the color space converter (CSC) must be
used to perform this conversion. When SCART support is
enabled, the parameters for the CSC are automatically
configured correctly for this operation.
If the user wishes to use a different conversion matrix, this
autoconfiguration can be disabled and the CSC can be manually
programmed. For details on this manual configuration, please
contact ADI.
0 (default)—The CSC is configured automatically for the RGB
to YPrPb conversion.
1—The CSC can be configured manually (not recommended).