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參數(shù)資料
| 型號： | ADV7188 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| 中文描述： | 標清多格式視頻解碼器支持快速開關重疊 |
| 文件頁數(shù)： | 48/112頁 |
| 文件大小： | 943K |
| 代理商： | ADV7188 |
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ADV7188
Rev. 0 | Page 48 of 112
0
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
VSYNC END
PVENDSIGN
ODD FIELD
0
1
NO
YES
PVENDDELO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVENDDELE
VSEHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 35. PAL VSYNC End
PVEND[4:0] PAL VSYNC End, Address 0xE9 [4:0]
The default value of PVEND is 10100, indicating the PAL
VSYNC end position.
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC on the VS pin are modified.
PFTOGDELO PAL Field Toggle Delay on Odd Field, Address
0xEA [7]
0 (default)—No delay.
1—Delays the F toggle/transition on an odd field by a line
relative to PFTOG.
PFTOGDELE PAL Field Toggle Delay on Even Field, Address
0xEA [6]
0 (default)—No delay.
1 (default)—Delays the F toggle/transition on an even field by a
line relative to PFTOG.
PFTOGSIGN PAL Field Toggle Sign, Address 0xEA [5]
0—Delays the field transition. Set for user manual
programming.
1 (default)—Advances the field transition. Not recommended
for user programming.
PFTOG PAL Field Toggle, Address 0xEA [4:0]
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
For all NTSC/PAL field timing controls, the F bit in the AV
code and the field signal on the FIELD/DE pin are modified.
0
ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
PFTOGSIGN
ODD FIELD
0
1
NO
YES
PFTOGDELE
ADDITIONAL
DELAY BY
1 LINE
1
0
PFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
1
0
FIELD
TOGGLE
NOT VALID FOR USER
PROGRAMMING
Figure 36. PAL F Toggle
SYNC PROCESSING
The ADV7188 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I
2
C bits.
ENHSPLL Enable HSYNC Processor, Address 0x01 [6]
The HSYNC processor is designed to filter incoming HSYNCs
that have been corrupted by noise, providing improved per-
formance for video signals with stable time bases but poor SNR.
0—Disables the HSYNC processor.
1 (default)—Enables the HSYNC processor.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7189B | Multiformat SDTV Video Decoder |
| ADV7189BBSTZ268H | Multiformat SDTV Video Decoder |
| ADV7189BKSTZ10F | Multiformat SDTV Video Decoder |
| ADV7189 | Multiformat SDTV Video Decoder |
| ADV7189KST | Multiformat SDTV Video Decoder |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7188BSTZ | 功能描述:IC DECODER VID MULTIFORM 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ | 功能描述:IC VIDEO DECODER SDTV 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189BBSTZ268H | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
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