- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375269 > ADV7188 (Analog Devices, Inc.) Multiformat SDTV Video Decoder with Fast Switch Overlay Support PDF資料下載
參數(shù)資料
| 型號： | ADV7188 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| 中文描述： | 標(biāo)清多格式視頻解碼器支持快速開關(guān)重疊 |
| 文件頁數(shù)： | 19/112頁 |
| 文件大小： | 943K |
| 代理商： | ADV7188 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
ADV7188
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
PDBP, Address 0x0F [2]
The digital core of the ADV7188 can be shut down by using a
pin (PWRDN) and the PWRDN bit. The PDBP register
controls which of the two has the higher priority. The default is
to give the pin (PWRDN) priority. This allows the user to have
the ADV7188 powered down by default.
Rev. 0 | Page 19 of 112
0 (default)—The digital core power is controlled by the
PWRDN pin (the bit is disregarded).
1—The bit has priority (the pin is disregarded).
PWRDN, Address 0x0F [5]
Setting the PWRDN bit switches the ADV7188 into a chip-wide
power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I
2
C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I
2
C interface itself is unaffected,
and remains operational in power-down mode.
The ADV7188 leaves the power-down state if the PWRDN bit is
set to 0 (via I
2
C), or if the overall part is reset using the RESET
pin. Note that PDBP must be set to 1 for the PWRDN bit to
power down the ADV7188.
0 (default)—The chip is operational.
1—The ADV7188 is in chip-wide power-down.
ADC Power-Down Control
The ADV7188 contains four 12-bit ADCs (ADC 0, ADC 1,
ADC 2 and ADC 3). If required, it is possible to power down
each ADC individually.
In CVBS mode, ADC1 and ADC2 should be powered
down to save on power consumption.
In S-Video mode, ADC2 should be powered down to save
on power consumption.
PWRDN_ADC_0, Address 0x3A [3]
0 (default)—The ADC is in normal operation.
1—ADC0 is powered down.
PWRDN_ADC_1, Address 0x3A [2]
0 (default)—The ADC is in normal operation.
1—ADC1 is powered down.
PWRDN_ADC_2, Address 0x3A [1]
0 (default)—The ADC is in normal operation.
1—ADC2 is powered down.
PWRDN_ADC_3, Address 0x3A [0]
0 (default)—The ADC is in normal operation.
1—ADC3 is powered down.
FB_PWRDN, Address 0x0F [1]
To achieve very low power-down current, it is necessary to
prevent activity on toggling input pins from reaching circuitry
that could consume current. FB_PWRDN gates signals from the
FB input pin.
0 (default)—The FB input is in normal operation.
1—The FB input is in power-save mode.
RESET CONTROL
RES Chip Reset, Address 0x0F [7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7188, issues a full chip reset. All I
2
C registers are reset to
their default values, making these bits self-clearing. Some
register bits do not have a reset value specified. They keep their
last written value. Those bits are marked as having a reset value
of x in the register tables. After the reset sequence, the part
immediately starts to acquire the incoming video signal.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before performing any more I
2
C
writes.
The I
2
C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented. See
the MPU Port Description section for a full description.
0 (default)—Operation is normal.
1—The reset sequence starts.
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the
ADV7188. Upon setting the TOD bit, the P19 to P0, HS, VS,
FIELD, and SFL pins are three-stated. The ADV7188 also
supports three-stating via a dedicated pin, OE. The output
drivers are three-stated if the TOD bit or the OE pin is set high.
The timing pins (HS/VS/FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the Three-State LLC Drivers and the Timing Signals Output
Enable sections. Individual drive strength controls are provided
by the DR_STR_XX bits.
0 (default)—The output drivers are enabled.
1—The output drivers are three-stated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7189B | Multiformat SDTV Video Decoder |
| ADV7189BBSTZ268H | Multiformat SDTV Video Decoder |
| ADV7189BKSTZ10F | Multiformat SDTV Video Decoder |
| ADV7189 | Multiformat SDTV Video Decoder |
| ADV7189KST | Multiformat SDTV Video Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7188BSTZ | 功能描述:IC DECODER VID MULTIFORM 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ | 功能描述:IC VIDEO DECODER SDTV 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189BBSTZ268H | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。