參數(shù)資料
型號(hào)： ADUC7061BCPZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 72/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計(jì)資源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
標(biāo)準(zhǔn)包裝： 5,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 66 of 108
TIMERS
The ADuC706x features four general-purpose timer/counters.
Timer0
Timer1 or wake-up timer
Timer2 or watchdog timer
Timer3
The four timers in their normal mode of operation can be either
free running or periodic.
In free running mode, the counter decrements/increments from
the maximum or minimum value until zero/full scale and starts
again at the maximum or minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale and
starts again at the value stored in the load register. Note that the
TxLD MMR should be configured before the TxCON MMR.
The timer interval is calculated as follows:
If the timer is set to count down then
Interval = (TxLD x Prescaler) / Source Clock
If the timer is set to count up then
Interval = ((Full Scale - TxLD) x Prescaler) / Source Clock.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time that the value
of the counter reaches zero (if counting down) or full scale (if
counting up). An IRQ can be cleared by writing any value to the
clear register of the particular timer (TxCLRI).
Table 78. Timer Event Capture
Bit
Description
0
Reserved
1
Timer0
2
Timer1 or wake-up timer
3
Timer2 or watchdog timer
4
Timer3
5
Reserved
6
Reserved
7
Reserved
8
ADC
9
UART
10
SPI
11
XIRQ0
12
XIRQ1
13
I2C master
14
I2C slave
15
PWM
16
XIRQ2 (GPIO IRQ2)
17
XIRQ3 (GPIO IRQ3)
HR:MIN:SEC: 1/128 FORMAT
To use the timer in Hr : Min : Sec : hundreds format the 32768
kHz clock and prescaler of 256 should be selected. The
hundreds field does not represent milliseconds but 1/128 of a
second (256/32768).The bits representing the Hour, minute and
second are not consecutive in the register. This arrangement
applies to TxLd and TxVAL when using the Hr : Min : Sec :
hundreds format as set in TxCON[5:4]. See Table 79 for more
details.
Table 79. Hr:Min:Sec: hundreds format
Bit
Value
Description
31:24
0 to 23 or 0 to 255
Hours
23:22
0
Reserved
21:16
0 to 59
Minutes
15:14
0
Reserved
13:8
0 to 59
Seconds
7
0
Reserved
6:0
0 to 127
1/128 of second
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