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參數(shù)資料
| 型號： | ADUC7061BCPZ32-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 49/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16/32BIT 32KB 32LFCSP |
| 產(chǎn)品變化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 設(shè)計資源： | USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 8 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 45 of 108
Table 43. ADC0CON MMR Bit Designations
Bit
Name
Description
15
ADC0EN
Primary channel ADC enable.
This bit is set to 1 by user code to enable the primary ADC.
Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR
to 0.
14:13
ADC0DIAG[1:0]
Diagnostic current source enable bits.
[00] = current sources off.
[01] = enables a 50 μA current source on the selected positive input (for example, ADC0).
[10] = enables a 50 μA current source on the selected negative input (for example, ADC1).
[11] = enables a 50 μA current source on both selected inputs (for example, ADC0 and ADC1).
12
HIGHEXTREF0
This bit must be set high if the external reference for ADC0 exceeds 1.35 V. This results in the reference source
being divided by 2.
Clear this bit when using the internal reference or an external reference of less than 1.35 V.
11
AMP_CM
This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2.
This bit is cleared to 0 by user code to set the PGA output common-mode voltage to the PGA input common-
mode voltage level.
10
ADC0CODE
Primary channel ADC output coding.
This bit is set to 1 by user code to configure primary ADC output coding as unipolar.
This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement.
9:6
ADC0CH[3:0]
Primary channel ADC input select.
[0000] = ADC0/ADC1 (differential mode).
[0001] = ADC0/ADC5 (single-ended mode).
[0010] = ADC1/ADC5 (single-ended mode).
[0011] = VREF+, VREF. Note: This is the reference selected by the ADC0REF bits.
[0100] = Not used. This bit combination is reserved for future functionality and should not be written.
[0101] = ADC2/ADC3 (differential mode).
[0110] = ADC2/ADC5 (single-ended mode).
[0111] = ADC3/ADC5 (single-ended mode).
[1000] = internal short to ADC1.
[1001] = internal short to ADC1.
5:4
ADC0REF[1:0]
Primary channel ADC reference select.
[00] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMDE[5].
[01] = external reference inputs (VREF+, VREF) selected. Set the HIGHEXTREF0 bit if the reference voltage
exceeds 1.3 V.
[10] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN) selected. Set the
HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V.
[11] = (AVDD, AGND) divide-by-two selected.
3:0
ADC0PGA[3:0].
Primary channel ADC gain select. Note, nominal primary ADC full-scale input voltage = (VREF/gain).
[0000] = ADC0 gain of 1. Buffer of negative input is bypassed.
[0001] = ADC0 gain of 2.
[0010] = ADC0 gain of 4 (default value). Enables the in-amp.
[0011] = ADC0 gain of 8.
[0100] = ADC0 gain of 16.
[0101] = ADC0 gain of 32.
[0110] = ADC0 gain of 64 (maximum PGA gain setting).
[0111] = ADC0 gain of 128 (extra gain implemented digitally).
[1000] = ADC0 gain of 256.
[1001] = ADC0 gain of 512.
[1XXX] = ADC0 gain is undefined.
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