參數(shù)資料
型號： ADUC7061BCPZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 106/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計(jì)資源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
標(biāo)準(zhǔn)包裝： 5,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 97 of 108
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
SPISTA Register
Name:
SPISTA
Address:
0xFFFF0A00
Default value:
0x00000000
Access:
Read only
Function:
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Table 107. SPISTA MMR Bit Designations
Bit
Name
Description
15:12
Reserved bits.
11
SPIREX
SPI receive FIFO excess bytes present. This bit is set when there are more bytes in the receive FIFO than
indicated in the SPIMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE.
10:8
SPIRXFSTA[2:0]
SPI receive FIFO status bits.
[000] = receive FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid bytes in the FIFO.
[011] = 3 valid bytes in the FIFO.
[100] = 4 valid bytes in the FIFO.
7
SPIFOF
SPI receive FIFO overflow status bit.
Set when the receive FIFO was already full when new data was loaded to the FIFO. This bit generates an
interrupt except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
6
SPIRXIRQ
SPI receive IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes has been received.
Cleared when the SPISTA register is read.
5
SPITXIRQ
SPI transmit IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes has been transmitted.
Cleared when the SPISTA register is read.
4
SPITXUF
SPI transmit FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the transmit FIFO. This bit generates an
interrupt except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
3:1
SPITXFSTA[2:0]
SPI transmit FIFO status bits.
[000] = transmit FIFO is empty.
[001] = 1 valid bytes in the FIFO.
[010] = 2 valid bytes in the FIFO.
[011] = 3 valid bytes in the FIFO.
[100] = 4 valid bytes in the FIFO.
0
SPIISTA
SPI interrupt status bit.
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
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