參數(shù)資料
型號： ADUC7061BCPZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 55/108頁
文件大小： 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計(jì)資源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
標(biāo)準(zhǔn)包裝： 5,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 50 of 108
Primary Channel ADC Data Register
Name:
ADC0DAT
Address:
0xFFFF051C
Default value:
0x00000000
Access:
Read only
Function:
This ADC data MMR holds the 24-bit
conversion result from the primary ADC. The
ADC does not update this MMR if the ADC0
conversion result ready bit (ADCSTA[0]) is
set. A read of this MMR by the MCU clears
all asserted ready flags (ADCSTA[1:0]).
Table 49. ADC0DAT MMR Bit Designations
Bit
Description
23:0
ADC0 24-bit conversion result.
Auxiliary Channel ADC Data Register
Name:
ADC1DAT
Address:
0xFFFF0520
Default value:
0x00000000
Access:
Read only
Function:
This ADC data MMR holds the 24-bit
conversion result from the auxiliary ADC.
The ADC does not update this MMR if the
ADC0 conversion result ready bit
(ADCSTA[1]) is set.
Table 50. ADC1DAT MMR Bit Designations
Bit
Description
23:0
ADC1 24-bit conversion result.
Primary Channel ADC Offset Calibration Register
Name:
ADC0OF
Address:
0xFFFF0524
Default value:
Part specific, factory programmed
Access:
Read and write
Function:
This ADC offset MMR holds a 16-bit offset
calibration coefficient for the primary ADC.
The register is configured at power-on with a
factory default value. However, this register
automatically overwrites if an offset
calibration of the primary ADC is initiated by
the user via bits in the ADCMDE MMR. User
code can write to this calibration register only
if the ADC is in idle mode. An ADC must be
enabled and in idle mode before being
written to any offset or gain register. The
ADC must be in idle mode for at least 23 s.
Table 51. ADC0OF MMR Bit Designations
Bit
Description
15:0
ADC0 16-bit offset calibration value.
Auxiliary Channel ADC Offset Calibration Register
Name:
ADC1OF
Address:
0xFFFF0528
Default value:
Part specific, factory programmed
Access:
Read and write
Function:
This offset MMR holds a 16-bit offset
calibration coefficient for the auxiliary
channel. The register is configured at power-
on with a factory default value. However, this
register is automatically overwritten if an
offset calibration of the auxiliary channel is
initiated by the user via bits in the ADCMDE
MMR. User code can write to this calibration
register only if the ADC is in idle mode. An
ADC must be enabled and in idle mode
before being written to any offset or gain
register. The ADC must be in idle mode for
at least 23 s.
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