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參數(shù)資料
| 型號： | ADUC7061BCPZ32-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 47/108頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 16/32BIT 32KB 32LFCSP |
| 產(chǎn)品變化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 設計資源： | USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) |
| 標準包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 8 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 43 of 108
ADC Interrupt Mask Register
Name:
ADCMSKI
Address:
0xFFFF0504
Default value:
0x0000
Access:
Read and write
Function:
This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the
same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled.
By default, all bits are 0, meaning all ADC interrupt sources are disabled.
Table 41. ADCMSKI MMR Bit Designations
Bit
Name
Description
7
Not used. This bit is reserved for future functionality and should not be monitored by user code.
6
ADC0ATHEX_INTEN
ADC0 accumulator comparator threshold exceeded interrupt enable bit.
When set to 1, this bit enables an interrupt when the ADC0ATHEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
5
Not used. This bit is reserved for future functionality and should not be monitored by user code.
4
ADC0THEX_INTEN
Primary channel ADC comparator threshold exceeded interrupt enable bit.
When set to 1, this bit enables an interrupt when the ADC0THEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
3
ADC0OVR_INTEN
When set to 1, this bit enables an interrupt when the ADC0OVR bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
2
Not used. This bit is reserved for future functionality and should not be monitored by user code.
1
ADC1RDY_INTEN
Auxiliary ADC result ready bit.
When set to 1, this bit enables an interrupt when the ADC1RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
0
ADC0RDY_INTEN
Primary ADC result ready bit.
When set to 1, this bit enables an interrupt when the ADC0RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
ADC Mode Register
Name:
ADCMDE
Address:
0xFFFF0508
Default value:
0x03
Access:
Read and write
Function:
The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem.
Table 42. ADCMDE MMR Bit Designations
Bit
Name
Description
7
ADCCLKSEL
Set this bit to 1 to enable ADCCLK = 512 kHz. This bit should be set for normal ADC operation.
Clear this bit to enable ADCCLK = 131 kHz. This bit should be cleared for low power ADC operation.
6
Not used. This bit is reserved for future functionality and should not be monitored by user code.
5
ADCLPMEN
Enable low power mode. This bit has no effect if ADCMDE[4:3] = 00 (ADC is in normal mode).
This bit must be set to 1 in low power mode.
Clearing this bit in low power mode results in erratic ADC results.
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