參數(shù)資料
型號(hào)： ADSP-21267
廠商： Analog Devices, Inc.
英文描述： Preliminary Technical Data
中文描述： 初步技術(shù)數(shù)據(jù)
文件頁(yè)數(shù)： 4/44頁(yè)
文件大小： 454K
代理商： ADSP-21267
Rev. PrA
|
Page 4 of 44
|
January 2004
ADSP-21267
PRELIMINARY TECHNICAL DATA
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multi-function instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general purpose data register file is contained in each process-
ing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21267 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see the
Figure 1 on page 1
). With the ADSP-21267’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
TheADSP-21267 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21267’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
Figure 2. ADSP-21267 System Sample Configuration
DAI
SPORT3
SPORT2
SPORT0
SCLK0
SFS0
SD0A
SD0B
SRU
DAI_P1
DAI_P2
DAI_P3
DAI_P18
DAI_P19
DAI_P20
DAC
(OPTIONAL)
ADC
(OPTIONAL)
FS
CLK
SDAT
FS
CLK
SDAT
3
CLOCK
2
2
CLKIN
XTAL
CLK_CFG1-0
BOOTCFG1-0
FLG3-1
ADDR
PARALLEL
PORT
RAM, ROM
BOOT ROM
I/O DEVICE
OE
WE
CS
DATA
RD
WR
CLKOUT
ALE
AD15-0
LATCH
RESET
JTAG
6
ADSP-21267
A
D
C
FLG0
PCGB
PCGA
CLK
FS
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