參數(shù)資料
型號： ADSP-21267
廠商： Analog Devices, Inc.
英文描述： Preliminary Technical Data
中文描述： 初步技術(shù)數(shù)據(jù)
文件頁數(shù)： 12/44頁
文件大?。?/td> 454K
代理商： ADSP-21267
Rev. PrA
|
Page 12 of 44
|
January 2004
ADSP-21267
PRELIMINARY TECHNICAL DATA
CLKIN
I
Input only
Local Clock In
. Used in conjunction with XTAL. CLKIN is the ADSP-21267 clock input.
It configures the ADSP-21267 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables
the internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the ADSP-21267 to use the external clock source
such as an external clock oscillator. The core is clocked either by the PLL output or
this clock input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted,
changed, or operated below the specified frequency.
Crystal Oscillator Terminal
. Used in conjunction with CLKIN to drive an external
crystal.
Core/CLKIN Ratio Control
. These pins set the start up clock frequency. See
Table 5
on page 13
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.
Reset Out/Local Clock Out
. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can
be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTL register. The default is reset out.
Processor Reset
. Resets the ADSP-21267 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
Test Clock (JTAG)
. Provides a clock for JTAG boundary scan. must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21267.
Test Mode Select (JTAG)
. Used to control the test state machine. TMS has a
22.5 k
internal pull-up resistor.
Test Data Input (JTAG)
. Provides serial data for the boundary scan logic. TDI has a
22.5 k
internal pull-up resistor.
Test Data Output (JTAG)
. Serial scan output of the boundary scan path.
Test Reset (JTAG)
. Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21267. TRST has
a 22.5 k
internal pull-up resistor.
Emulation Status
. Must be connected to the ADSP-21267 Analog Devices DSP
Tools product line of JTAG emulators target board connector only. EMU has a
22.5 k
internal pullup resistor.
Core Power Supply
. Nominally +1.2 V dc and supplies the DSP’s core processor (13
pins on the BGA package, 32 pins on the LQFP package).
I/O Power Supply
. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the
LQFP package).
Analog Power Supply
. Nominally +1.2 V dc and supplies the DSP’s internal PLL
(clock generator). This pin has the same specifications as V
DDINT
, except that added
filtering circuitry is required.
For more information, see Power Supplies on page 7.
Analog Power Supply Return
.
Power Supply Return
. (54 pins on the BGA package, 39 pins on the LQFP package).
XTAL
O
Output only
2
CLKCFG1-0
I
Input only
RSTOUT/CLKOUT
O
Output only
RESET
I/A
Input only
TCK
I
Input only
3
TMS
I/S
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state
4
Three-state with
pull-up enabled
TDI
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
Three-state with
pull-up enabled
V
DDINT
P
V
DDEXT
P
A
VDD
P
A
VSS
GND
G
G
1
RD, WR, and ALE are continuously driven by the DSP and won’t be three-stated.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is three-state driver with both output path.
4
Three-state is three-state driver.
Table 2. Pin Descriptions (Continued)
Pin
Type
State During &
After Reset
Function
相關(guān)PDF資料
PDF描述
ADSP-21267SKBCZ-X Preliminary Technical Data
ADSP-21267SKSTZ-X Preliminary Technical Data
ADSP-21362 SHARC Processor
ADSP-21362BBC-1AA SHARC Processor
ADSP-21362BBCZ-1AA SHARC Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21267SKBCZ-X 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data
ADSP-21267SKSTZ-X 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data
ADSP-21362 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
adsp-21362bbc-1aa 制造商:Analog Devices 功能描述:
ADSP-21362BBCZ-1AA 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 333 MHz Processor includes DTCP/SPDIF RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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