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參數(shù)資料
| 型號： | ADSP-21267 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Preliminary Technical Data |
| 中文描述： | 初步技術數(shù)據(jù) |
| 文件頁數(shù)： | 3/44頁 |
| 文件大?。?/td> | 454K |
| 代理商： | ADSP-21267 |
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ADSP-21267
Rev. PrA
|
Page 3 of 44
|
January 2004
PRELIMINARY TECHNICAL DATA
GENERAL DESCRIPTION
The ADSP-21267 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices' Super Har-
vard Architecture. The ADSP-21267 is source code compatible
with the ADSP-2136x, and ADSP-2116x DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. Like other SHARC DSPs,
the ADSP-21267 is a 32-bit/40-bit floating-point processor opti-
mized for high performance audio applications with its dual-
ported on-chip SRAM, mask-programmable ROM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
Digital Audio Interface (DAI).
As shown in the Functional Block Diagram on page 1, the
ADSP-21267 uses two computational units to deliver a signifi-
cant performance increase over previous SHARC processors on
a range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the ADSP-21267 DSP achieves an
instruction cycle time of 6.6 ns at 150 MHz. With its SIMD
computational hardware, the ADSP-21267 can perform 900
MFLOPS running at 150 MHz.
Table 1
shows performance benchmarks for the ADSP-21267.
The ADSP-21267 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 1M bit dual-ported SRAM memory, 3M bits
dual-ported ROM, an I/O processor that supports 18 DMA
channels, four serial ports, an SPI interface, an external parallel
bus, and Digital Audio Interface (DAI).
The block diagram of the ADSP-21267
on page 1
, illustrates the
following architectural features:
Two processing elements, each containing an ALU, Multi-
plier, Shifter and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
Three Programmable Interval Timers with PWM Genera-
tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities
On-Chip dual-ported SRAM (1 Mbit)
On-Chip dual-ported, mask-programmable ROM
(3 Mbits)
JTAG test access port
8- or 16-bit Parallel port that supports interfaces to off-chip
memory peripherals
DMA controller
Four full-duplex serial ports
SPI-compatible interface
Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), four serial
ports, eight serial interfaces, a 20-bit synchronous parallel
input port, 10 interrupts, six flag outputs, six flag inputs,
three timers, and a flexible signal routing unit (SRU)
Figure 2 on page 4
shows one sample configuration of a SPORT
using the precision clock generator to interface with an I
2
S ADC
and an I
2
S DAC with a much lower jitter clock than the serial
port would generate itself. Many other SRU configurations are
possible.
ADSP-21267 FAMILY CORE ARCHITECTURE
The ADSP-21267 is code compatible at the assembly level with
the ADSP-2136x, ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-21267 shares architec-
tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21267 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive audio algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Table 1. ADSP-21267 Benchmarks (at 150 MHz)
Benchmark Algorithm
Speed
(at 150 MHz)
61.3 μ
s
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
1
IIR Filter (per biquad)
1
Matrix Multiply (pipelined)
[3x3] x [3x1]
[4x4] x [4x1]
Divide (y/x)
Inverse Square Root
1
Assumes two files in multichannel SIMD mode.
3.3 ns
13.3 ns
30 ns
53.3 ns
20 ns
30 ns
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21267SKBCZ-X | Preliminary Technical Data |
| ADSP-21267SKSTZ-X | Preliminary Technical Data |
| ADSP-21362 | SHARC Processor |
| ADSP-21362BBC-1AA | SHARC Processor |
| ADSP-21362BBCZ-1AA | SHARC Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21267SKBCZ-X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21267SKSTZ-X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21362 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| adsp-21362bbc-1aa | 制造商:Analog Devices 功能描述: |
| ADSP-21362BBCZ-1AA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 333 MHz Processor includes DTCP/SPDIF RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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