
Preliminary Technical Data
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
Processor
ADSP-21267
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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Tel:781/329-4700
www.analog.com
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Code compatible with all other SHARC DSPs
The ADSP-21267 processes high performance audio while
enabling low system costs
Audio decoders and post processor-algorithms support.
Non-volatile memory can be configured to contain a com-
bination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2,
Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES
Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others.
See www.analog.com/SHARC for a complete list
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O —a parallel port, an SPI port, four serial
ports, a digital audio interface (DAI) and JTAG test port
DAI incorporates two precision clock generators (PCG), and
an input data port (IDP) that includes a parallel data acqui-
sition port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—1M Bit of on-chip SRAM and a dedicated
3M Bits of on-chip mask-programmable ROM
The ADSP-21267 is available with a 150 MHz core instruction
rate. For complete ordering information, see
Ordering
Guide on page43
Figure 1. FUNCTIONAL BLOCK DIAGRAM
ADDR
DATA
PX REGISTER
6
JTAG TEST & EMULATION
20
3
SERIAL PORTS (6)
INPUT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
TIMERS (3)
SIGNAL
ROUTING
UNIT
PRECISION CLOCK
GENERATORS (2)
DIGITAL AUDIO INTERFACE
3
16
ADDRE SS/
DATA BUS/ GP IO
CONTROL/G PIO
PARALLEL
PORT
IOP
(MEREGISTERS
CONTROL,
DSTATUS, &
4
SPI PORT (1)
DMA CONTROLLER
22 CHANNELS
4
IRQ/TIMEXP
I/O PROCESSOR
PELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4X32
DAG2
8X4X32
32
PM ADDRESS BUS
DM ADDRESS BUS
32
PM DATA BUS
DM DATA BUS
64
64
CORE PROCESSOR
PROGRAM
SEQUENCER
ADDR
DATA
SRAM
0.5 MBIT
ROM
1.5 MBIT
DUAL PBLOCK 0
DUAL PBLOCK 1
S
IOD
(32)
IOA
(18)
SRAM
ROM
1.5 MBIT