參數(shù)資料
型號(hào)： ADSP-21267
廠商： Analog Devices, Inc.
英文描述： Preliminary Technical Data
中文描述： 初步技術(shù)數(shù)據(jù)
文件頁(yè)數(shù)： 32/44頁(yè)
文件大?。?/td> 454K
代理商： ADSP-21267
Rev. PrA
|
Page 32 of 44
|
January 2004
ADSP-21267
PRELIMINARY TECHNICAL DATA
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 27
. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the
ADSP-2126x Hardware Reference Manual
. Note
that the most significant 16 bits of external PDAP data can be
provided through either the parallel port AD[15:0] or the
DAI_P[20:5] pins. The remaining 4 bits can only be sourced
through DAI_P[4:1]. The timing below is valid at the
DAI_P[20:1] pins or at the AD[15:0] pins.
Table 27. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
t
SPCLKEN
t
HPCLKEN
t
PDSD
t
PDHD
t
PDCLKW
t
PDCLK
Min
Max
Unit
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
1
Clock Width
Clock Period
2.5
2.5
2.5
2.5
7
20
ns
ns
ns
ns
ns
ns
Switching Characteristics
t
PDHLDD
t
PDSTRB
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
2 x t
CCLK
1 x t
CCLK
– 1
ns
ns
1
Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
Figure 24. PDAP Timing
DAI_P[20:1]
(PDAP_CLK)
SAMPLE EDGE
t
PDSD
t
PDHD
t
SPCLKEN
t
HPCLKEN
t
PDCLKW
DATA
DAI_P[20:1]
(PDAP_CLKEN)
t
PDSTRB
t
PDHLDD
DAI_P[20:1]
(PDAP_STROBE)
相關(guān)PDF資料
PDF描述
ADSP-21267SKBCZ-X Preliminary Technical Data
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21267SKBCZ-X 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data
ADSP-21267SKSTZ-X 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data
ADSP-21362 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
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