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參數(shù)資料
型號(hào)： AD9549ABCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 56/76頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
AD9549
Rev. D | Page 6 of 76
AC SPECIFICATIONS
fS= 1 GHz, DAC RSET = 10 kΩ, power supply pins within the range specified in the DC Specifications section, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUTS
Pin 12, Pin 13, Pin 15, and Pin 16
Frequency Range (Sine Wave)
10
750
MHz
Minimum recommended slew rate: 40 V/μs
Frequency Range (CMOS)
0.008
50
MHz
Frequency Range (LVPECL)
0.008
725
MHz
Frequency Range (LVDS)
0.008
725
MHz
LVDS must be ac-coupled; lower frequency bound may
be higher, depending on the size of the decoupling
capacitor
Minimum Slew Rate
0.04
V/ns
Minimum Pulse Width High
620
ps
Minimum Pulse Width Low
620
ps
FDBK_IN INPUT
Pin 40, Pin 41
Input Frequency Range
10
400
MHz
Minimum Differential Input Level
225
mV p-p
12 dBm into 50 ; must be ac-coupled
Minimum Slew Rate
40
V/μs
SYSTEM CLOCK INPUT
Pin 27, Pin 28
SYSCLK PLL Bypassed
Input Frequency Range
250
1000
MHz
Maximum fOUT is 0.4 × fSYSCLK
Duty Cycle
45
55
%
Minimum Differential Input Level
632
mV p-p
0 dBm into 50
SYSCLK PLL Enabled
VCO Frequency Range, Low Band
700
810
MHz
When in the range, use the low VCO band exclusively
VCO Frequency Range, Auto Band
810
900
MHz
When in the range, use the VCO Auto band select
VCO Frequency Range, High Band
900
1000
MHz
When in the range, use the high VCO band exclusively
Maximum Input Rate of System Clock PFD
200
MHz
Without SYSCLK PLL Doubler
Input Frequency Range
11
200
MHz
Multiplication Range
4
66
Integer multiples of 2, maximum PFD rate and system
clock frequency must be met
Minimum Differential Input Level
632
mV p-p
0 dBm into 50
With SYSCLK PLL Doubler
Input Frequency Range
6
100
MHz
Multiplication Range
8
132
Integer multiples of 8
Input Duty Cycle
50
%
Deviating from 50% duty cycle may adversely affect
spurious performance.
Minimum Differential Input Level
632
mV p-p
0 dBm into 50
Crystal Resonator with SYSCLK PLL Enabled
Crystal Resonator Frequency Range
10
50
MHz
AT cut, fundamental mode resonator
Maximum Crystal Motional Resistance
100
See the
SYSCLK Inputs section for recommendations
CLOCK DRIVERS
HSTL Output Driver
Frequency Range
20
725
MHz
See
Figure 12 for maximum toggle rate
Duty Cycle
48
52
%
Rise Time/Fall Time (20-80%)
115
165
ps
100 termination across OUT/OUTB, 2 pF load
Jitter (12 kHz to 20 MHz)
1.0
ps
fIN = 19.44 MHz, fOUT = 155.52 MHz. 50 MHz system
clock input (see
Figure 3 to Figure 11 for test conditions)
HSTL Output Driver with 2× Multiplier
Frequency Range
400
725
MHz
Duty Cycle
45
55
%
Rise Time/Fall Time (20% to 80%)
115
165
ps
100 termination across OUT/OUTB, 2 pF load
Subharmonic Spur Level
35
dBc
Without correction
Jitter (12 kHz to 20 MHz)
1.1
ps
fIN = 19.44 MHz, fOUT = 622.08 MHz, 50 MHz system
clock input (see
Figure 3 to Figure 11 for test conditions)
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