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參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 45 of 76
Read
If the instruction word is for a read operation (I15 = 1), the next
N × 8 SCLK cycles clock out the data from the address specified
in the instruction word, where N is 1, 2, 3, 4, as determined by
[W1:W0]. In this case, 4 is used for streaming mode where four
or more words are transferred per read. The data readback is
valid on the falling edge of SCLK.
The default mode of the AD9549 serial control port is bidirec-
tional mode, and the data readback appears on the SDIO pin. It
is possible to set the AD9549 to unidirectional mode by writing
to the SDO active bit at Register 0x0000[7] = 0; in that mode,
the requested data appears on the SDO pin.
By default, a read request reads the register value that is currently
in use by the AD9549. However, setting Register 0x0004[0] = 1
causes the buffered registers to be read instead. The buffered
registers are the ones that take effect during the next I/O update.
06744-
052
AD9549
CORE
UPDATE
REGISTERS
TOGGLE
IO_UPDATE
PIN
SCLK
SDIO
SDO
CSB
SERIAL
CONTROL
PORT
C
ON
TR
OL
R
E
GIS
TE
R
S
RE
G
IS
T
E
R
BUF
F
E
RS
Figure 52. Relationship Between Serial Control Port Register Buffers and
Control Registers of the AD9549
The AD9549 uses Register 0x0000 to Register 0x0509. Although
the AD9549 serial control port allows both 8-bit and 16-bit
instructions, the 8-bit instruction mode provides access to only
five address bits ([A4:A0]), which restricts its use to Address
Space 0x0000 to Address Space 0x0031. The AD9549 defaults
to 16-bit instruction mode on power-up, and 8-bit instruction
mode is not supported.
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates whether
the instruction is a read or a write. The next two bits, [W1:W0],
are the transfer length in bytes. The final 13 bits are the address
([A12:A0]) at which to begin the read or write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], which is interpreted
according to Table 10.
Bits[A12:A0] select the address within the register map that is
written to or read from during the data transfer portion of the
communications cycle. The AD9549 uses all of the 13-bit address
space. For multibyte transfers, this address is the starting byte
address.
Table 10. Byte Transfer Count
W1
W0
Bytes to Transfer
(Excluding the 2-Byte Instruction)
0
1
0
1
2
1
0
3
1
Streaming mode
MSB/LSB FIRST TRANSFERS
The AD9549 instruction word and byte data may be MSB first
or LSB first. The default for the AD9549 is MSB first. The LSB
first mode can be set by writing a 1 to Register 0x0000[6] and
requires that an I/O update be executed. Immediately after the
LSB first bit is set, all serial control port operations are changed
to LSB first order.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from high address to low address.
In MSB first mode, the serial control port internal address
generator decrements for each data byte of the multibyte
transfer cycle.
When LSB first = 1 (LSB first), the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The serial control port internal byte address
generator increments for each byte of the multibyte transfer cycle.
The AD9549 serial control port register address decrements
from the register address just written toward 0x0000 for multi-
byte I/O operations if the MSB first mode is active (default).
If the LSB first mode is active, the serial control port register
address increments from the address just written toward 0x1FFF
for multibyte I/O operations.
Unused addresses are not skipped during multibyte I/O operations.
The user should write the default value to a reserved register and
should write only 0s to unmapped registers. Note that it is more
efficient to issue a new write command than to write the default
value to more than two consecutive reserved (or unmapped)
registers.
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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