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參數(shù)資料
| 型號(hào)： | AD9549ABCPZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 49/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 53 of 76
I/O REGISTER DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)
Register 0x0000—Serial Configuration
Table 14.
Bits
Bit Name
Description
[7:4]
These bits are the mirror image of Bits[3:0].
3
Long instruction
Read-only. The AD9549 supports only long instructions.
2
Soft reset
Resets register map, except for Register 0x0000. Setting this bit forces a soft reset, meaning that S1 to S4
are not tristated, nor is their state read when this bit is cleared. The AD9549 assumes the values of S1 to S4
that were present during the last hard reset. This bit is not self-clearing, and all other registers are restored
to their default values after a soft reset.
1
LSB first
Sets bit order for serial port.
1 = LSB first.
0 = MSB first. I/O update must occur for MSB first to take effect.
0
SDO active
Enables SDO pin.
1 = SDO pin enabled (4-wire serial port mode).
0 = 3-wire mode.
Register 0x0001—Reserved
Register 0x0002 and Register 0x0003—Part ID (Read Only)
Register 0x0004—Serial Options
Table 15.
Bits
Bit Name
Description
0
Read buffer register
For buffered registers, serial port readback reads from actual (active) registers instead of the buffer.
1 = reads the buffered values that take effect during the next I/O update.
0 = reads values that are currently in effect.
Register 0x0005—Serial Options (Self-Clearing)
Table 16.
Bits
Bit Name
Description
0
Register update
Software access to the register update pin function. Writing a 1 to this bit is identical to performing an I/O
update.
POWER-DOWN AND RESET (REGISTER 0x0010 TO REGISTER 0x0013)
Register 0x0010—Power-Down and Enable
Power-up default is defined by the startup pins.
Table 17.
Bits
Bit Name
Description
7
PD HSTL driver
Power down HSTL output driver.
1 = HSTL driver powered down.
6
Enable CMOS driver
Power up CMOS output driver.
1 = CMOS driver on.
5
Enable output doubler
Power up output clock generator doubler. Output doubler must still be enabled in Register 0200.
4
PD SYSCLK PLL
System clock multiplier power-down.
1 = system clock multiplier powered down.
3
PD REFA
Power-down reference clock A input (and related circuits).
2
PD REFB
Power-down reference clock B input (and related circuits).
1
Full PD
Setting this bit is identical to activating the PD pin and puts all blocks (except serial port) into power-down
mode. SYSCLK is turned off.
0
Digital PD
Remove clock from most of digital section; leave serial port usable. In contrast to full PD, setting this bit
does not debias inputs, allowing for quick wake-up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類(lèi)型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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