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參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 29 of 76
When calculating frequency error for a hitless switchover
environment such as Stratum 3, as defined in Telcordia
GR-1244-CORE, the designer must consider the frequency
error budget for the entire system. The frequency disturbance
caused by a reference clock switchover in the AD9549
contributes to this budget.
It is also critical that the designer differentiate between appli-
cations that require the output clock to track the input clock,
as opposed to applications that require the PLL to smooth out
transient disturbances on the input.
Based on all of the preceding considerations, the AD9549
digital PLL architecture allows the designer to choose a loop
bandwidth tailored to meet the requirements for a given
application. The loop bandwidth can range from 0.1 Hz up
to 100 kHz, provided that the loop bandwidth is never more
than 1/10th of the phase detector frequency.
HOLDOVER
Holdover Control and Frequency Accuracy
Holdover functionality provides the user with a means of
maintaining the output clock signal even in the absence of a
reference signal at the REFA or REFB input. In holdover mode,
the output clock is generated from the SYSCLK input (via the
DDS) by directly applying a frequency tuning word to the DDS.
The frequency accuracy of the AD9549 is exactly the frequency
accuracy of the system clock input.
Transfer from normal operation to holdover mode can be
accomplished either manually or automatically by appropriately
programming the automatic holdover bit (Register 0x01C0, Bit 0,
0 = manual, 1 = auto). The actual transfer to holdover operation,
however, depends on the state of the HOLDOVER pin and the
state of the enable holdover override and holdover on/off
control register bits (Register 0x01C1, Bits 1:0).
Manual holdover is established when the automatic holdover bit is
a Logic 0 (default). In manual mode, holdover is determined by
the state of the HOLDOVER pin (0 = normal, 1 = holdover). The
HOLDOVER pin is configured as a high impedance (>100 kΩ)
input pin to accommodate manual holdover operation.
Automatic holdover is invoked when the automatic holdover bit
is a Logic 1. In automatic mode, the HOLDOVER pin is configured
as a low impedance output with its logic state indicating the
holdover state as determined by the internal state machine
(0 = normal, 1 = holdover).
In automatic holdover operation, the user can override the internal
state machine by programming the enable holdover override bit
to a Logic 1 and the holdover mode bit (Register 0x001C0[4])
to the desired state (0 = normal, 1 = holdover). However, the
HOLDOVER pin does not indicate the forced holdover state in
the override condition but continues to indicate the holdover
state as chosen by the internal state machine (even though the
state machine choice is overridden). This allows the user to
force a holdover state by means of the programming registers
while monitoring the response of the state machine via the
HOLDOVER pin. A diagram of the reference switchover and
holdover logic is shown in Figure 33.
Note that the default state for the reference switchover bits is as
follows: automatic holdover = 0, enable holdover override = 0,
and holdover mode = 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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