參數(shù)資料
型號(hào)： AD9549ABCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/76頁(yè)
文件大小： 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
AD9549
Rev. D | Page 30 of 76
06744-
037
4
3
2
1
RESET
FAILA & VALIDB & AUTOREFSEL & OVRDREFPIN
FAILB & VALIDA & AUTOREFSEL & OVRDREFPIN
REFB
&
HOLDOVER
REFA
&
HOLDOVER
REFB
&
HOLDOVER
REFA
&
HOLDOVER
V
AL
IDB
&
AUT
O
RCO
V
&
O
V
RDHL
DP
IN
V
AL
IDA
&
AUT
O
RCO
V
&
O
V
RDHL
DP
IN
FAI
LA
&
V
AL
IDB
&
AUT
O
RE
FS
EL
&
AUT
O
RCO
V &
O
VRDRE
FP
IN
&
O
VRDHL
DP
IN
FAI
LB
&
V
AL
IDA
&
AUT
O
RE
FS
EL
&
AUT
O
RCO
V &
O
VRDRE
FP
IN
&
O
VRDHL
DP
IN
F
AI
L
A
&
AUT
O
HO
L
D
&
O
V
RDHL
DP
IN
&
(V
AL
IDB
O
R
AUT
O
RE
F
S
E
L
O
R
O
V
RDRE
F
P
IN)
F
AI
L
B
&
AUT
O
HO
L
D
&
O
V
RDHL
DP
IN
&
(V
AL
IDA
O
R
AUT
O
RE
F
S
E
L
O
R
O
V
RDRE
F
P
IN)
REFA:
REFB:
HOLDOVER:
FAILA:
FAILB:
VALIDA:
VALIDB:
REFERENCE A SELECTED
REFERENCE B SELECTED
HOLDOVER STATE
REFERENCE A FAILED
REFERENCE B FAILED
REFERENCE A VALIDATED
REFERENCE B VALIDATED
OVRDREFPIN:
OVRDHLDPIN:
AUTOREFSEL:
AUTORCOV:
AUTOHOLD:
||:
&:
%:
OVERRIDE REF SEL PIN
OVERRIDE HOLDOVER PIN
AUTOMATIC REFERENCE SELECT
AUTOMATIC HOLDOVER RECOVERY
AUTOMATIC HOLDOVER ENTRY
LOGICAL OR
LOGICAL AND
LOGICAL NOT
ABBREVIATION KEY
Figure 37. Holdover State Diagram
Holdover and Reference Switchover State Machine
Figure 37 shows the interplay between the input reference
signals and holdover, as well as the various control signals
and the four states.
State 1 or State 2 is in effect when the device is not in the holdover
condition, and State 3 or State 4 is in effect when the holdover
condition is active. When REFA is selected as the active reference,
State 1 or State 3 is in effect. When REFB is selected as the active
reference, State 2 or State 4 is in effect. A transition between states
depends on the reference switchover and holdover control register
settings, the logic state of the REFSELECT and HOLDOVER
pins, and the occurrence of certain events (for example, a reference
failure).
The state machine and its relationship to control register and
external pin stimuli are shown in Figure 37. The state machine
generates a derived reference selection and holdover state. The
actual control signal sent to the reference switchover logic and
the holdover logic, however, depends on the control signals
applied to the muxes. The dashed path leading to the REFSELECT
and HOLDOVER pins is active when the automatic mode is
selected for reference selection and/or holdover assertion.
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