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參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 20 of 76
06744-
025
DAC
(14-BIT)
ANGLE TO
AMPLITUDE
CONVERSION
14
19
48
14
PHASE
OFFSET
Q
D
48-BIT ACCUMULATOR
FREQUENCY
TUNING WORD
(FTW)
fS
I-SET
DAC+
DAC–
Figure 25. DDS Block Diagram
The null points imply the existence of transmission zeros placed
at finite frequencies. While transmission zeros placed at infinity
yield minimal phase delay, zeros placed closer to dc result in
increased phase delay. Hence, the position of the first null point
has a significant impact on the phase delay introduced by the CCI
filter. This is an important consideration because excessive phase
delay negatively impacts the overall closed-loop response. As
a rule of thumb, choose a value for P so that the frequency of
the first null point (fS/P) is the greater of 80× the desired loop
bandwidth or 1.5× the frequency of CLK (fR/R).
The value of P thus calculated (PMAX) is the largest usable value
in practice. Because P is programmed as PIO, it is necessary to
define PMAX in terms of PIO so that PIOMAX can be determined.
The condition PIO ≤ PIOMAX ensures that the impact of the phase
delay of the CCI filter on the phase margin of the loop does not
exceed 5°. PIOMAX can be expressed as
=
REF
S
LOOP
S
IOMAX
f
P
3
2
log
floor
,
80
log
floor
,
16
min
,
5
max
2
With a properly chosen value for P, the closed-loop response of
the digital PLL is primarily determined by the response of the
digital loop filter. Flexibility in controlling the loop filter response
translates directly into flexibility in the range of applications
satisfied by the architecture of the AD9549.
The AD9549 evaluation software automatically sets the value of
the P-divider based on the user’s input criteria. Therefore, the
formulas are provided here mainly to assist in understanding
how the part works.
Direct Digital Synthesizer (DDS)
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (fS) that serves
as the fundamental timing source of the DDS. The accumulator
behaves as a modulo-248 counter with a programmable step size
that is determined by the FTW. A block diagram of the DDS is
shown in Figure 25.
The input to the DDS is a 48-bit FTW that provides the
accumulator with a seed value. On each cycle of fS, the accumulator
adds the value of the FTW to the running total of its output.
For example, given FTW = 5, the accumulator counts in
increments of 5 sec, incrementing on each fS cycle. Over time,
the accumulator reaches the upper end of its capacity (248 in this
case), at which point, it rolls over, retaining the excess. The average
rate at which the accumulator rolls over establishes the frequency of
the output sinusoid. The average rollover rate of the accumulator
is given by the following equation and establishes the output
frequency (fDDS) of the DDS:
S
DDS
f
FTW
f
=
48
2
Solving this equation for FTW yields
=
S
DDS
f
FTW
48
2
round
For example, given that fS = 1 GHz and fDDS = 19.44 MHz, then
FTW = 5,471,873,547,255 (0x04FA05143BF7).
The relative phase of the sinusoid can be controlled numerically,
as well. This is accomplished using the phase offset input to the
DDS (a programmable 14-bit value (Δphase); see the I/O Register
Map section). The resulting phase offset, ΔΦ (radians), is given by
π
=
14
2
phase
Φ
The DDS can be operated in either open-loop or closed-loop
mode, via the close loop bit in the PLL control register
(Register 0x0100, Bit 0).
There are two open-loop modes: single tone and holdover. In
single-tone mode, the DDS behaves like a frequency synthesizer
and uses the value stored in the FTW0 register to determine its
output frequency. Alternatively, the FTW and Δphase values can be
determined by the device itself using the frequency estimator.
Because single-tone mode ignores the reference inputs, it is very
useful for generating test signals to aid in debugging. Single tone
mode must be activated manually via register programming.
Note that due to the internal architecture of the AD9549, the
LSB of the 48-bit tuning word becomes a don’t care when
operating the DDS in single-tone mode. This results in an
effective frequency resolution of 7 Hz with the DAC system
clock equal to 1 GHz.
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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