- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9674 > AD9549ABCPZ (Analog Devices Inc)IC CLOCK GEN/SYNCHRONIZR 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/76頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
AD9549
Rev. D | Page 35 of 76
External Loop Filter (SYSCLK PLL)
The loop bandwidth of the SYSCLK PLL multiplier can be
adjusted by means of three external components, as shown in
Figure 44. The nominal gain of the VCO is 800 MHz/V. The
recommended component values are shown in Table 7. They
establish a loop bandwidth of approximately 1.6 MHz with
the charge pump current set to 250 μA. The default case is
N = 40 and assumes a 25 MHz SYSCLK input frequency and
generates an internal DAC sampling frequency (fS) of 1 GHz.
06744-
044
CHARGE
PUMP
~2pF
LOOP_FILTER
C2
R1
C1
EXTERNAL
LOOP FILTER
VCO
AD9549
FERRITE
BEAD
AVDD
29
26
31
Figure 44. External Loop Filter for SYSCLK PLL
Table 7. Recommended Loop Filter Values for a Nominal
1.5 MHz SYSCLK PLL Loop Bandwidth
Multiplier
R1
Series C1
Shunt C2
<8
390
1 nF
82 pF
10
470
820 pF
56 pF
20
1 k
390 pF
27 pF
40 (default)
2.2 k
180 pF
10 pF
60
2.7 k
120 pF
5 pF
Detail of SYSCLK Differential Inputs
A diagram of the SYSCLK input pins is provided in Figure 45.
Included are details of the internal components used to bias the
input circuitry. These components have a direct effect on the static
levels at the SYSCLK input pins. This information is intended to
aid in determining how best to interface to the device for a given
application.
Note that the SYSCLK PLL bypassed and SYSCLK PLL enabled
input paths are internally biased to a dc level of ~1 V. Care should
be taken to ensure that any external connections do not disturb
the dc bias because this may significantly degrade performance.
Generally, it is recommended that the SYSCLK inputs be
ac-coupled to the signal source (except when using a crystal
resonator).
HARMONIC SPUR REDUCTION
The most significant spurious signals produced by the DDS are
harmonically related to the desired output frequency of the DDS.
The source of these harmonic spurs can usually be traced to the
DAC, and the spur level is in the 60 dBc range. This ratio
represents a level that is about 10 bits below the full-scale
output of the DAC (10 bits down is 210, or 1/1024).
To reduce such a spur requires combining the original signal with
a replica of the spur, but offset in phase by 180°. This idea is the
foundation of the technique used to reduce harmonic spurs in
the AD9549. Because the DAC has 14-bit resolution, a 60dBc
spur can be synthesized using only the lower four bits of the DAC
full-scale range. That is, the 4 LSBs can create an output level that
is approximately 60 dB below the full-scale level of the DAC
(commensurate with a 60 dBc spur). This fact gives rise to
a means of digitally reducing harmonic spurs or their aliased
images in the DAC output spectrum by digitally adding a sinusoid
at the input of the DAC with similar magnitude as the offending
spur but shifted in phase to produce destructive interference.
06744-
045
500
500
~1.5pF
INTERNAL
CLOCK
VSS
~1V
VSS
~2pF
+
SYSCLK PLL BYPASSED
1k
1k
~3pF
INTERNAL
CLOCK
VSS
~1V
VSS
~2pF
+
SYSCLK PLL ENABLED
AMP
INTERNAL
CLOCK
CRYSTAL RESONATOR WITH
SYSCLK PLL ENABLED
MUX
SYSCLK
SYSCLKB
Figure 45. Differential SYSCLK Inputs
Although the worst spurs tend to be harmonic in origin, the fact
that the DAC is part of a sampled system results in the possibility
of some harmonic spurs appearing in nonharmonic locations in
the output spectrum. For example, if the DAC is sampled at 1 GHz
and generates an output sinusoid of 170 MHz, the fifth harmonic
would normally be at 850 MHz. However, because of the sampling
process, this spur appears at 150 MHz, only 20 MHz away from
the fundamental. Hence when attempting to reduce DAC spurs,
it is important to know the actual location of the harmonic spur
in the DAC output spectrum based on the DAC sample rate so
that its harmonic number can be reduced.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADN2814ACPZ | IC CLOCK/DATA RECOVERY 32LFCSP |
| SM802105UMG | IC SYNTHESIZER 2CH 24-QFN |
| SM802104UMG | IC SYNTHESIZER 2CH 24-QFN |
| SM843001-212KA | IC CLK SYNTHESIZER FIBRE 8-TSSOP |
| MS27466T25F4S | CONN RCPT 56POS WALL MT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。