- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364551 > 8XC552 (NXP Semiconductors N.V.) 80C51 FAMILY DERIVATIVES PDF資料下載
參數(shù)資料
| 型號： | 8XC552 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大小： | 382K |
| 代理商： | 8XC552 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
9
CTI0
BIT
SYMBOL
FUNCTION
TM2IR.7
TM2IR.6
TM2IR.5
TM2IR.4
TM2IR.3
TM2IR.2
TM2IR.1
TM2IR.0
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
Timer T2 16-bit overflow interrupt flag
CM2 interrupt flag
CM1 interrupt flag
CM0 interrupt flag
CT3 interrupt flag
CT2 interrupt flag
CT1 interrupt flag
CT0 interrupt flag
SU00761
CTI1
CTI2
CTI3
CMI0
CMI1
CMI2
T2OV
0
1
2
3
4
5
6
7
(LSB)
(MSB)
TM2IR (C8H)
Interrupt Flag Register (TM2IR)
PCT0
BIT
SYMBOL
FUNCTION
IP1.7
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
Timer T2 overflow interrupt(s) priority level
Timer T2 comparator 2 interrupt priority level
Timer T2 comparator 1 interrupt priority level
Timer T2 comparator 0 interrupt priority level
Timer T2 capture register 3 interrupt priority level
Timer T2 capture register 2 interrupt priority level
Timer T2 capture register 1 interrupt priority level
Timer T2 capture register 0 interrupt priority level
PCT1
PCT2
PCT3
PCM0
PCM1
PCM2
PT2
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IP1 (F8H)
Timer 2 Interrupt Priority Register (IP1)
Figure 8. Interrupt Flag Register (TM2IR) and Timer T2 Interrupt Priority Register (IP1)
Timer T3, The Watchdog Timer
In addition to Timer T2 and the standard timers, a watchdog timer is
also incorporated on the 8XC552. The purpose of a watchdog timer
is to reset the microcontroller if it enters erroneous processor states
(possibly caused by electrical noise or RFI) within a reasonable
period of time. An analogy is the “dead man’s handle” in railway
locomotives. When enabled, the watchdog circuitry will generate a
system reset if the user program fails to reload the watchdog timer
within a specified length of time known as the “watchdog interval.”
Watchdog Circuit Description:
The watchdog timer (Timer T3)
consists of an 8-bit timer with an 11-bit prescaler as shown in Figure
9. The prescaler is fed with a signal whose frequency is 1/12 the
oscillator frequency (1MHz with a 12MHz oscillator). The 8-bit timer
is incremented every “t” seconds, where:
t = 12
×
2048
×
1/f
OSC
(= 1.5ms at f
OSC
= 16MHz; = 1ms at f
OSC
= 24MHz)
If the 8-bit timer overflows, a short internal reset pulse is generated
which will reset the 8XC552. A short output reset pulse is also
generated at the RST pin. This short output pulse (3 machine
cycles) may be destroyed if the RST pin is connected to a capacitor.
This would not, however, affect the internal reset operation.
Watchdog operation is activated when external pin EW is tied low.
When EW is tied low, it is impossible to disable the watchdog
operation by software.
How to Operate the Watchdog Timer:
The watchdog timer has to
be reloaded within periods that are shorter than the programmed
watchdog interval; otherwise the watchdog timer will overflow and a
system reset will be generated. The user program must therefore
continually execute sections of code which reload the watchdog
timer. The period of time elapsed between execution of these
sections of code must never exceed the watchdog interval. When
using a 16MHz oscillator, the watchdog interval is programmable
between 1.5ms and 392ms. When using a 24MHz oscillator, the
watchdog interval is programmable between 1ms and 255ms.
In order to prepare software for watchdog operation, a programmer
should first determine how long his system can sustain an
erroneous processor state. The result will be the maximum
watchdog interval. As the maximum watchdog interval becomes
shorter, it becomes more difficult for the programmer to ensure that
the user program always reloads the watchdog timer within the
watchdog interval, and thus it becomes more difficult to implement
watchdog operation.
The programmer must now partition the software in such a way that
reloading of the watchdog is carried out in accordance with the above
requirements. The programmer must determine the execution times
of all software modules. The effect of possible conditional branches,
subroutines, external and internal interrupts must all be taken into
account. Since it may be very difficult to evaluate the execution
times of some sections of code, the programmer should use worst
case estimations. In any event, the programmer must make sure
that the watchdog is not activated during normal operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8XL51FB | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
| 8XL51FC | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
| 8XL51FA | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
| 8XL54 | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
| 8XL58 | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8XC562 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 FAMILY DERIVATIVES |
| 8XC58 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 8XC80C32 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit CMOS (low voltage, low power and high speed) microcontroller families |
| 8XF0016-S3P | 制造商:XFMRS 制造商全稱:XFMRS Inc. 功能描述:INDUCTOR |
| 8XF0106-S3P | 制造商:XFMRS 制造商全稱:XFMRS Inc. 功能描述:INDUCTOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。