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參數(shù)資料
| 型號： | 8XC552 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 41/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC552 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
41
Reset Circuitry
The reset circuitry for the 8XC552 is connected to the reset pin RST.
A Schmitt trigger is used at the input for noise rejection (see
Figure 25). The output of the Schmitt trigger is sampled by the reset
circuitry every machine cycle.
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (24 oscillator periods) while the oscillator is
running. The CPU responds by executing an internal reset. During
reset, ALE and PSEN output a HIGH level. In order to perform a
correct reset, this level must not be affected by external elements.
The RST line can also be pulled HIGH internally by a pull-up
transistor activated by the watchdog timer T3. The length of the
output pulse from T3 is 3 machine cycles. A pulse of such short
duration is necessary in order to recover from a processor or system
fault as fast as possible.
Note that the short reset pulse from Timer T3 cannot discharge the
power-on reset capacitor (see Figure 26). Consequently, when the
watchdog timer is also used to set external devices, this capacitor
arrangement should not be connected to the RST pin, and a
different circuit should be used to perform the power-on reset
operation. A timer T3 overflow, if enabled, will force a reset condition
to the 8XC552 by an internal connection, whether the output RST is
tied LOW or not.
V
DD
R
RST
RST
Schmitt
Trigger
Reset
Circuitry
On-chip
resistor
Overflow
timer T3
Figure 25. On-Chip Reset Configuration
R
RST
V
DD
V
DD
+
2.2
μ
F
8XC552
RST
Figure 26. Power-On Reset
The internal reset is executed during the second cycle in which RST
is HIGH and is repeated every cycle until RST goes low. It leaves
the internal registers as follows:
RESGISTER
CONTENT
ACC
ADCON
ADCH
B
CML0-CML2
CMH0-CMH2
CTCON
CTL0-CTL3
CTH0-CTH3
DPL
DPH
IEN0
IEN1
IP0
IP1
PCH
PCL
PCON
PSW
PWM0
PWM1
PWMP
P0-P4
PS
RTE
S0BUF
S0CON
S1ADR
S1CON
S1DAT
S1STA
SP
STE
TCON
TH0, TH1
TMH2
TL0, TL1
TML2
TMOD
TM2CON
TM2IR
T3
0000
xx00
xxxx
0000
0000
0000
0000
xxxx
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0xx0
0000
0000
0000
0000
1111
xxxx
0000
xxxx
0000
0000
0000
0000
1111
0000
1100
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
xxxx
0000
0000
0000
0000
xxxx
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
xxxx
0000
xxxx
0000
0000
0000
0000
1000
0111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
The internal RAM is not affected by reset. At power-on, the RAM
content is indeterminate.
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