參數(shù)資料
型號(hào)： 8XC552
廠商： NXP Semiconductors N.V.
英文描述： 80C51 FAMILY DERIVATIVES
中文描述： 80C51系列衍生物
文件頁(yè)數(shù)： 42/60頁(yè)
文件大小： 382K
代理商： 8XC552
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
42
Interrupts
The 8XC552 has fifteen interrupt sources, each of which can be
assigned one of two priority levels, as shown in Figure 27. The five
interrupt sources common to the 80C51 are the external interrupts
(INT0 and INT1), the timer 0 and timer 1 interrupts (IT0 and IT1),
and the serial I/O interrupt (RI or TI). In the 8XC552, the standard
serial interrupt is called SIO0. Since the subsystems which create
these interrupts are identical on both parts, their functionality is
likewise identical. The only differences are the locations of the
enable and priority register configurations and the priority structure.
This is detailed below along with the specifics of the interrupts
unique to the 8XC552.
The eight Timer T2 interrupts are generated by flags CTI0-CT13,
CMI0-CMI2, and by the logical OR of flags T2OV and T2BO. Flags
CTI0 to CT13 are set by input signals CT0I to CT3i. Flags CMI0 to
CMI2 are set when a match occurs between Timer T2 and the
compare registers CM0, CM1, and CM2. When an 8-bit or 16-bit
overflow occurs, flags T2BO and T2OV are set, respectively. These
nine flags are not cleared by hardware and must be reset by
software to avoid recurring interrupts.
The ADC interrupt is generated by the ADCI flag in the ADC control
register (ADCON). This flag is set when an ADC conversion result is
ready to be read. ADCI is not cleared by hardware and must be
reset by software to avoid recurring interrupts.
The SIO1 (I
2
C) interrupt is generated by the SI flag in the SIO1
control register (S1CON). This flag is set when S1STA is loaded
with a valid status code.
The ADCI flag may be reset by software. It cannot be set by
software. All other flags that generate interrupts may be set or
cleared by software, and the effect is the same as setting or
resetting the flags by hardware. Thus, interrupts may be generated
by software and pending interrupts can be canceled by software.
Interrupt Enable Registers:
Each interrupt source can be
individually enabled or disabled by setting or clearing a bit in the
interrupt enable special function registers IEN0 and IEN1. All
interrupt sources can also be globally enabled or disabled by setting
or clearing bit EA in IEN0. The interrupt enable registers are
described in Figures 28 and 29.
Interrupt Priority Structure:
Each interrupt source can be assigned
one of two priority levels. Interrupt priority levels are defined by the
interrupt priority special function registers IP0 and IP1. IP0 and IP1
are described in Figures 30 and 31.
Interrupt priority levels are as follows:
“0”—low priority
“1”—high priority
A low priority interrupt may be interrupted by a high priority interrupt.
A high priority interrupt cannot be interrupted by any other interrupt
source. If two requests of different priority occur simultaneously, the
high priority level request is serviced. If requests of the same priority
are received simultaneously, an internal polling sequence
determines which request is serviced. Thus, within each priority
level, there is a second priority structure determined by the polling
sequence. This second priority structure is shown in Table 8.
The above Priority Within Level structure is only used when there
are simultaneous requests of the same priority level.
Interrupt Handling:
The interrupt sources are sampled at S5P2 of
every machine cycle. The samples are polled during the following
machine cycle. If one of the flags was in a set condition at S5P2 of
the previous machine cycle, the polling cycle will find it and the
interrupt system will generate an LCALL to the appropriate service
routine, provided this hardware-generated LCALL is not blocked by
any of the following conditions:
1. An interrupt of higher or equal priority level is already in
progress.
2. The current machine cycle is not the final cycle in the execution
of the instruction in progress. (No interrupt request will be
serviced until the instruction in progress is completed.)
3. The instruction in progress is RETI or any access to the interrupt
priority or interrupt enable registers. (No interrupt will be serviced
after RETI or after a read or write to IP0, IP1, IE0, or IE1 until at
least one other instruction has been subsequently executed.)
The polling cycle is repeated with every machine cycle, and the
values polled are the values present at S5P2 of the previous
machine cycle. Note that if an interrupt flag is active but is not being
responded to because of one of the above conditions, and if the flag
is inactive when the blocking condition is removed, then the blocked
interrupt will not be serviced. Thus, the fact that the interrupt flag
was once active but not serviced is not remembered. Every polling
cycle is new.
The processor acknowledges an interrupt request by executing a
hardware-generated LCALL to the appropriate service routine. In
some cases it also clears the flag which generated the interrupt, and
in others it does not. It clears the Timer 0, Timer 1, and external
interrupt flags. An external interrupt flag (IEO or IE1) is cleared only
if it was transition-activated. All other interrupt flags are not cleared
by hardware and must be cleared by the software. The LCALL
pushes the contents of the program counter on to the stack (but it
does not save the PSW) and reloads the PC with an address that
depends on the source of the interrupt being vectored to as shown
in Table 9.
Execution proceeds from the vector address until the RETI
instruction is encountered. The RETI instruction clears the “priority
level active” flip-flop that was set when this interrupt was
acknowledged. It then pops the top two bytes from the stack and
reloads the program counter. Execution of the interrupted program
continues from where it was interrupted.
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