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| 型號： | 8XC552 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC552 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
17
The Status Register, S1STA:
S1STA is an 8-bit read-only special
function register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined SIO1 states. When each of
these states is entered, a serial interrupt is requested (SI = “1”). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
More Information on SIO1 Operating Modes:
The four operating
modes are:
– Master Transmitter
– Master Receiver
– Slave Receiver
– Slave Transmitter
Data transfers in each mode of operation are shown in Figures
17–37. These figures contain the following abbreviations:
Abbreviation
S
SLA
R
W
A
A
Data
P
Explanation
Start condition
7-bit slave address
Read bit (high level at SDA)
Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level at SDA)
8-bit data byte
Stop condition
In Figures 17-37, circles are used to indicate when the serial
interrupt flag is set. The numbers in the circles show the status code
held in the S1STA register. At these points, a service routine must
be executed to continue or complete the serial transfer. These
service routines are not critical since the serial transfer is suspended
until the serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in S1STA
is used to branch to the appropriate service routine. For each status
code, the required software action and details of the following serial
transfer are given in Tables 3-7.
Master Transmitter Mode:
In the master transmitter mode, a
number of data bytes are transmitted to a slave receiver (see
Figure 17). Before the master transmitter mode can be entered,
S1CON must be initialized as follows:
S1CON (D8H)
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
7
6
5
4
3
2
1
0
1
0
0
0
X
bit rate
bit
rate
CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to
logic 1 to enable SIO1. If the AA bit is reset, SIO1 will not
acknowledge its own slave address or the general call address in
the event of another device becoming master of the bus. In other
words, if AA is reset, SIO0 cannot enter a slave mode. STA, STO,
and SI must be reset.
The master transmitter mode may now be entered by setting the
STA bit using the SETB instruction. The SIO1 logic will now test the
I
2
C bus and generate a start condition as soon as the bus becomes
free. When a START condition is transmitted, the serial interrupt flag
(SI) is set, and the status code in the status register (S1STA) will be
08H. This status code must be used to vector to an interrupt service
routine that loads S1DAT with the slave address and the data
direction bit (SLA+W). The SI bit in S1CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted
and an acknowledgment bit has been received, the serial interrupt
flag (SI) is set again, and a number of status codes in S1STA are
possible. There are 18H, 20H, or 38H for the master mode and also
68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The
appropriate action to be taken for each of these status codes is
detailed in Table 3. After a repeated start condition (state 10H). SIO1
may switch to the master receiver mode by loading S1DAT with
SLA+R).
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