
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
3
EXTERNAL
(FFFFH) 64K
(2000H) 8192
(1FFFH) 8191
(0000H) 0
INTERNAL
(EA = 1)
EXTERNAL
(EA = 0)
PROGRAM MEMORY
(FFFFH) 64K
(0000H) 0
EXTERNAL
DATA MEMORY
(FFH) 255
(00H) 0
INTERNAL
DATA RAM
SPECIAL
FUNCTION
REGISTERS
(7FH) 127
INTERNAL
DATA MEMORY
SU00754
OVERLAPPED
SPACE
Figure 1. Memory Map
Timer T2
Timer T2 is a 16-bit timer consisting of two registers TMH2 (HIGH
byte) and TML2 (LOW byte). The 16-bit timer/counter can be
switched off or clocked via a prescaler from one of two sources:
f
OSC
/12 or an external signal. When Timer T2 is configured as a
counter, the prescaler is clocked by an external signal on T2 (P1.4).
A rising edge on T2 increments the prescaler, and the maximum
repetition rate is one count per machine cycle (1MHz with a 12MHz
oscillator).
The maximum repetition rate for Timer T2 is twice the maximum
repetition rate for Timer 0 and Timer 1. T2 (P1.4) is sampled at
S2P1 and again at S5P1 (i.e., twice per machine cycle). A rising
edge is detected when T2 is LOW during one sample and HIGH
during the next sample. To ensure that a rising edge is detected, the
input signal must be LOW for at least 1/2 cycle and then HIGH for at
least 1/2 cycle. If a rising edge is detected before the end of S2P1,
the timer will be incremented during the following cycle; otherwise it
will be incremented one cycle later. The prescaler has a
programmable division factor of 1, 2, 4, or 8 and is cleared if its
division factor or input source is changed, or if the timer/counter is
reset.
Timer T2 may be read “on the fly” but possesses no extra read
latches, and software precautions may have to be taken to avoid
misinterpretation in the event of an overflow from least to most
significant byte while Timer T2 is being read. Timer T2 is not
loadable and is reset by the RST signal or by a rising edge on the
input signal RT2, if enabled. RT2 is enabled by setting bit T2ER
(TM2CON.5).
When the least significant byte of the timer overflows or when a
16-bit overflow occurs, an interrupt request may be generated.
Either or both of these overflows can be programmed to request an
interrupt. In both cases, the interrupt vector will be the same. When
the lower byte (TML2) overflows, flag T2B0 (TM2CON) is set and
flag T20V (TM2IR) is set when TMH2 overflows. These flags are set
one cycle after an overflow occurs. Note that when T20V is set,
T2B0 will also be set. To enable the byte overflow interrupt, bits ET2
(IEN1.7, enable overflow interrupt, see Figure 2) and T2IS0
(TM2CON.6, byte overflow interrupt select) must be set. Bit TWB0
(TM2CON.4) is the Timer T2 byte overflow flag.
To enable the 16-bit overflow interrupt, bits ET2 (IE1.7, enable
overflow interrupt) and T2IS1 (TM2CON.7, 16-bit overflow interrupt
select) must be set. Bit T2OV (TM2IR.7) is the Timer T2 16-bit
overflow flag. All interrupt flags must be reset by software. To enable
both byte and 16-bit overflow, T2IS0 and T2IS1 must be set and two
interrupt service routines are required. A test on the overflow flags
indicates which routine must be executed. For each routine, only the
corresponding overflow flag must be cleared.
Timer T2 may be reset by a rising edge on RT2 (P1.5) if the Timer
T2 external reset enable bit (T2ER) in T2CON is set. This reset also
clears the prescaler. In the idle mode, the timer/counter and
prescaler are reset and halted. Timer T2 is controlled by the
TM2CON special function register (see Figure 3).