參數(shù)資料
型號(hào)： 8XC552
廠商： NXP Semiconductors N.V.
英文描述： 80C51 FAMILY DERIVATIVES
中文描述： 80C51系列衍生物
文件頁(yè)數(shù)： 46/60頁(yè)
文件大小： 382K
代理商： 8XC552
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
46
I/O Port Structure
The 8XC552 has six 8-bit ports. Each port consists of a latch
(special function registers P0 to P5), an input buffer, and an output
driver (port 0 to 4 only). Ports 0-3 are the same as in the 80C51,
with the exception of the additional functions of port 1. The parallel
I/O function of port 4 is equal to that of ports 1, 2, and 3. Port 5 may
be used as an input port only.
Figure 32 shows the bit latch and I/O buffer functional diagrams of
the unique 8XC552 ports. A bit latch corresponds to one bit in a
port’s SFR and is represented as a D type flip-flop. A “write to latch”
signal from the CPU latches a bit from the internal bus and a “read
latch” signal from the CPU places the Q output of the flip-flop on the
internal bus. A “read pin” signal from the CPU places the actual port
pin level on the internal bus. Some instructions that read a port read
the actual port pin levels, and other instructions read the latch (SFR)
contents.
Port 1 Operation
Port 1 operates the same as it does in the 8051 with the exception
of port lines P1.6 and P1.7, which may be selected as the SCL and
SDA lines of serial port SIO1 (I
2
C). Because the I
2
C bus may be
active while the device is disconnected from V
DD
, these pins are
provided with open drain drivers. Therefore pins P1.6 and P1.7 do
not have internal pull-ups.
Port 5 Operation
Port 5 may be used to input up to 8 analog signals to the ADC.
Unused ADC inputs may be used to input digital inputs. These
inputs have an inherent hysteresis to prevent the input logic from
drawing excessive current from the power lines when driven by
analog signals. Channel to channel crosstalk (Ct) should be taken
into consideration when both analog and digital signals are
simultaneously input to Port 5 (see, D.C. characteristics in data
sheet).
Port 5 is not bidirectional and may not be configured as an output
port. All six ports are multifunctional, and their alternate functions
are listed in Table 10. A more detailed description of these features
can be found in the relevant parts of this section.
Pulse Width Modulated Outputs
The 8XC552 contains two pulse width modulated output channels
(see Figure 33). These channels generate pulses of programmable
length and interval. The repetition frequency is defined by an 8-bit
prescaler PWMP, which supplies the clock for the counter. The
prescaler and counter are common to both PWM channels. The 8-bit
counter counts modulo 255, i.e., from 0 to 254 inclusive. The value
of the 8-bit counter is compared to the contents of two registers:
PWM0 and PWM1. Provided the contents of either of these registers
is greater than the counter value, the corresponding PWM0 or
PWM1 output is set LOW. If the contents of these registers are
equal to, or less than the counter value, the output will be HIGH. The
pulse-width-ratio is therefore defined by the contents of the registers
PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1
and may be programmed in increments of 1/255.
Buffered PWM outputs may be used to drive DC motors. The
rotation speed of the motor would be proportional to the contents of
PWMn. The PWM outputs may also be configured as a dual DAC. In
this application, the PWM outputs must be integrated using
conventional operational amplifier circuitry. If the resulting output
voltages have to be accurate, external buffers with their own analog
supply should be used to buffer the PWM outputs before they are
integrated. The repetition frequency f
PWM
, at the PWMn outputs is
give by:
f
PWM
f
OSC
PWMP)
2
(1
255
This gives a repetition frequency range of 123Hz to 31.4kHz (f
OSC
=
16MHz). At fosc = 24MHz, the frequency range is 184Hz to 47.1Hz.
By loading the PWM registers with either 00H or FFH, the PWM
channels will output a constant HIGH or LOW level, respectively.
Since the 8-bit counter counts modulo 255, it can never actually
reach the value of the PWM registers when they are loaded with
FFH.
When a compare register (PWM0 or PWM1) is loaded with a new
value, the associated output is updated immediately. It does not
have to wait until the end of the current counter period. Both PWMn
output pins are driven by push-pull drivers. These pins are not used
for any other purpose.
Prescaler frequency control register PWMP
PWMP (FEH)
7
6
5
4
3
2
1
0
MSB
LSB
PWMP.0-7
Prescaler division factor = PWMP + 1.
Reading PWMP gives the current reload value. The actual count of
the prescaler cannot be read.
PWM0 (FCH)
PWM1 (FDH)
7
6
5
4
3
2
1
0
MSB
LSB
PWM0/1.0-7} Low/high ratio of PWMn
(PWMn)
255
(PWMn)
Analog-to-Digital Converter
The analog input circuitry consists of an 8-input analog multiplexer
and a 10-bit, straight binary, successive approximation ADC. The
analog reference voltage and analog power supplies are connected
via separate input pins. The conversion takes 50 machine cycles,
i.e., 37.5
μ
s at an oscillator frequency of 16MHz, 25
μ
s at an oscillator
frequency of 24MHz. Input voltage swing is from 0V to +5V.
Because the internal DAC employs a ratiometric potentiometer,
there are no discontinuities in the converter characteristic. Figure 34
shows a functional diagram of the analog input circuitry.
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