參數(shù)資料
型號(hào)： 8XC552
廠商： NXP Semiconductors N.V.
英文描述： 80C51 FAMILY DERIVATIVES
中文描述： 80C51系列衍生物
文件頁(yè)數(shù)： 7/60頁(yè)
文件大?。?/td> 382K
代理商： 8XC552
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
7
INT
INT
CT0
CT1
CT2
CT3
CTI0
INT
CT0I
CTI1
CT1I
CTI2
CT2I
CTI3
CT3I
1/12
Prescaler
T2 Counter
8-bit overflow interrupt
16-bit overflow interrupt
External reset
enable
off
f
osc
T2
RT2
T2ER
COMP
CMO (S)
INT
COMP
CM1 (R)
INT
COMP
CM2 (T)
INT
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
R
R
R
R
R
R
T
T
S
S
S
S
S
S
TG
TG
STE
RTE
I/O port 4
S
R
T
TG =
=
=
=
set
reset
toggle
toggle status
INT
TML2
TMH2
=
=
lower 8 bits
higher 8 bits
T2 SFR address:
SU00757
Figure 4. Block Diagram of Timer 2
Measuring Time Intervals Using Capture Registers:
When a
recurring external event is represented in the form of rising or falling
edges on one of the four capture pins, the time between two events
can be measured using Timer T2 and a capture register. When an
event occurs, the contents of Timer T2 are copied into the relevant
capture register and an interrupt request is generated. The interrupt
service routine may then compute the interval time if it knows the
previous contents of Timer T2 when the last event occurred. With a
12MHz oscillator, Timer T2 can be programmed to overflow every
524ms. When event interval times are shorter than this, computing
the interval time is simple, and the interrupt service routine is short.
For longer interval times, the Timer T2 extension routine may be
used.
Compare Logic:
Each time Timer T2 is incremented, the contents
of the three 16-bit compare registers CM0, CM1, and CM2 are
compared with the new counter value of Timer T2. When a match is
found, the corresponding interrupt flag in TM2IR is set at the end of
the following cycle. When a match with CM0 occurs, the controller
sets bits 0-5 of port 4 if the corresponding bits of the set enable
register STE are at logic 1.
When a match with CM1 occurs, the controller resets bits 0-5 of port
4 if the corresponding bits of the reset/toggle enable register RTE
are at logic 1 (see Figure 6 for RTE register function). If RTE is “0”,
then P4.n is not affected by a match between CM1 or CM2 and
Timer 2. When a match with CM2 occurs, the controller “toggles”
bits 6 and 7 of port 4 if the corresponding bits of the RTE are at
logic 1. The port latches of bits 6 and 7 are not toggled.
Two additional flip-flops store the last operation, and it is these
flip-flops that are toggled.
Thus, if the current operation is “set,” the next operation will be
“reset” even if the port latch is reset by software before the “reset”
operation occurs. The first “toggle” after a chip RESET will set the
port latch. The contents of these two flip-flops can be read at STE.6
and STE.7 (corresponding to P4.6 and P4.7, respectively). Bits
STE.6 and STE.7 are read only (see Figure 7 for STE register
function). A logic 1 indicates that the next toggle will set the port
latch; a logic 0 indicates that the next toggle will reset the port latch.
CM0, CM1, and CM2 are reset by the RST signal.
The modified port latch information appears at the port pin during
S5P1 of the cycle following the cycle in which a match occurred. If
the port is modified by software, the outputs change during S1P1 of
the following cycle. Each port 4 bit can be set or reset by software at
any time. A hardware modification resulting from a comparator
match takes precedence over a software modification in the same
cycle. When the comparator results require a “set” and a “reset” at
the same time, the port latch will be reset.
Timer T2 Interrupt Flag Register TM2IR:
Eight of the nine Timer
T2 interrupt flags are located in special function register TM2IR (see
Figure 8). The ninth flag is TM2CON.4.
The CT0I and CT1I flags are set during S4 of the cycle in which the
contents of Timer T2 are captured. CT0I is scanned by the interrupt
logic during S2, and CT1I is scanned during S3. CT2I and CT3I are
set during S6 and are scanned during S4 and S5. The associated
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