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參數(shù)資料
| 型號： | 8XC552 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 51/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC552 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
51
EOC
SOC
Reset SAR
Start of Conversion
End of Conversion
[Bit Pointer] = MSB
[Bit]
n
= 1
Conversion Time
Test
Complete
[Bit]
n
= 0
[Bit Pointer] + 1
Test Bit
Pointer
1
0
END
END
Figure 36. A/D Conversion Flowchart
(MSB)
(LSB)
AADR2
AADR1
AADR0
7
6
5
4
3
2
1
0
ADCON (C5H)
ADCON.7
ADCON.6
ADCON.5
ADC.1
ADC.0
ADEX
Bit 1 of ADC result
Bit 0 of ADC result
Enable external start of conversion by STADC
0 = Conversion can be started by software only (by setting ADCS)
1 = Conversion can be started by software or externally (by a rising edge on STADC)
ADC interrupt flag: this flag is set when an A/D conversion result is ready to be read. An interrupt is invoked if it is enabled. The flag may
be cleared by the interrupt service routine. While this flag is set, the ADC cannot start a new conversion. ADCI cannot be set by software.
ADC start and status: setting this bit starts an A/D conversion. It may be set by software or by the external signal STADC. The ADC logic
ensures that this signal is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset immediately after the interrupt
flag has been set. ADCS cannot be reset by software. A new conversion may not be started while either ADCS or ADCI is high.
Bit
Symbol
Function
ADEX
ADCI
ADCS
ADC.1
ADC.0
ADCON.4
ADCI
ADCON.3
ADCS
ADCI
ADCS
ADC Status
0
0
1
1
0
1
0
1
ADC not busy; a conversion can be started
ADC busy; start of a new conversion is blocked
Conversion completed; start of a new conversion requires ADCI=0
Conversion completed; start of a new conversion requires ADCI=0
ADCON.2
ADCON.1
ADCON.0
AADR2
AADR1
AADR0
Analogue input select: this binary coded address selects one of the
eight analogue port bits of P5 to be input to the converter. It can only
be changed when ADCI and ADCS are both LOW.
AADR2
AADR1
Selected Analog Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ADC0 (P5.0)
ADC1 (P5.1)
ADC2 (P5.2)
ADC3 (P5.3)
ADC4 (P5.4)
ADC5 (P5.5)
ADC6 (P5.6)
ADC7 (P5.7)
AADR0
0
1
0
1
0
1
0
1
If ADCI is cleared by software while ADCS is set at the same time, a new A/D conversion with the same channel number may be started.
But it is recommended to reset ADCI
before
ADCS is set.
Figure 37. ADC Control Register (ADCON)
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