
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
8
interrupt requests are recognized during the following cycle. If these
flags are polled, a transition at CT0I or CT1I will be recognized one
cycle before a transition on CT2I or CT3I since registers are read
during S5. The CMI0, CMI1, and CMI2 flags are set during S6 of the
cycle following a match. CMI0 is scanned by the interrupt logic
during S2; CMI1 and CMI2 are scanned during S3 and S4. A match
will be recognized by the interrupt logic (or by polling the flags) two
cycles after the match takes place.
The 16-bit overflow flag (T2OV) and the byte overflow flag (T2BO)
are set during S6 of the cycle in which the overflow occurs. These
flags are recognized by the interrupt logic during the next cycle.
Special function register IP1 (Figure 8) is used to determine the
Timer T2 interrupt priority. Setting a bit high gives that function a
high priority, and setting a bit low gives the function a low priority.
The functions controlled by the various bits of the IP1 register are
shown in Figure 8.
CTP0
BIT
SYMBOL
CAPTURE/INTERRUPT ON:
CTCON.7
CTCON.6
CTCON.5
CTCON.4
CTCON.3
CTCON.2
CTCON.1
CTCON.0
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
Capture Register 3 triggered by a falling edge on CT3I
Capture Register 3 triggered by a rising edge on CT3I
Capture Register 2 triggered by a falling edge on CT2I
Capture Register 2 triggered by a rising edge on CT2I
Capture Register 1 triggered by a falling edge on CT1I
Capture Register 1 triggered by a rising edge on CT1I
Capture Register 0 triggered by a falling edge on CT0I
Capture Register 0 triggered by a rising edge on CT0I
SU00758
CTN1
CTP1
CTN1
CTP2
CTN2
CTP3
CTN3
0
1
2
3
4
5
6
7
(LSB)
(MSB)
CTCON (EBH)
Figure 5. Capture Control Register (CTCON)
RP40
BIT
SYMBOL
FUNCTION
RTE.7
RTE.6
RTE.5
RTE.4
RTE.3
RTE.2
RTE.1
RTE.0
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
If “1” then P4.7 toggles on a match between CM1 and Timer T2
If “1” then P4.6 toggles on a match between CM1 and Timer T2
If “1” then P4.5 is reset on a match between CM1 and Timer T2
If “1” then P4.4 is reset on a match between CM1 and Timer T2
If “1” then P4.3 is reset on a match between CM1 and Timer T2
If “1” then P4.2 is reset on a match between CM1 and Timer T2
If “1” then P4.1 is reset on a match between CM1 and Timer T2
If “1” then P4.0 is reset on a match between CM1 and Timer T2
SU00759
RO41
RP42
RP43
RP44
RP45
TP46
TP47
0
1
2
3
4
5
6
7
(LSB)
(MSB)
RTE (EFH)
Figure 6. Reset/Toggle Enable Register (RTE)
SP40
BIT
SYMBOL
FUNCTION
STE.7
STE.6
STE.5
STE.4
STE.3
STE.2
STE.1
STE.0
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
Toggle flip-flops
Toggle flip-flops
If “1” then P4.5 is set on a match between CM0 and Timer T2
If “1” then P4.4 is set on a match between CM0 and Timer T2
If “1” then P4.3 is set on a match between CM0 and Timer T2
If “1” then P4.2 is set on a match between CM0 and Timer T2
If “1” then P4.1 is set on a match between CM0 and Timer T2
If “1” then P4.0 is set on a match between CM0 and Timer T2
SU00760
SP41
SP42
SP43
SP44
SP45
TG46
TG47
0
1
2
3
4
5
6
7
(LSB)
(MSB)
STE (EEH)
Figure 7. Set Enable Register (STE)