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參數(shù)資料
| 型號： | 8XC552 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 44/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC552 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
44
EX0
BIT
SYMBOL
FUNCTION
IEN0.7
EA
Global enable/disable control
0 = No interrupt is enabled
1 = Any individually enabled interrupt will be accepted
Eanble ADC interrupt
Enable SIO1 (I
2
C) interrupt
Enable SIO0 (UART) interrupt
Enable Timer 1 interrupt
Enable External interrupt 1
Enable Timer 0 interrupt
Enable External interrupt 0
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
EAD
ES1
ES0
ET1
EX1
ET0
EX0
SU00762
ET0
EX1
ET1
ES0
ES1
EAD
EA
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IEN0 (A8H)
Figure 28. Interrupt Enable Register (IEN0)
ECT0
BIT
SYMBOL
FUNCTION
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
Enable Timer T2 overflow interrupt(s)
Enable T2 Comparator 2 interrupt
Enable T2 Comparator 1 interrupt
Enable T2 Comparator 0 interrupt
Enable T2 Capture register 3 interrupt
Enable T2 Capture register 2 interrupt
Enable T2 Capture register 1 interrupt
Enable T2 Capture register 0 interrupt
SU00755
ECT1
ECT2
ECT3
ECM0
ECM1
ECM2
ET2
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IEN1 (E8H)
In all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled.
Figure 29. Interrupt Enable Register (IEN1)
PX0
BIT
SYMBOL
FUNCTION
IP0.7
IP0.6
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
–
PAD
PS1
PS0
PT1
PX1
PT0
PX0
Unused
ADC interrupt priority level
SIO1 (I
2
C) interrupt priority level
SIO0 (UART) interrupt priority level
Timer 1 interrupt priority level
External interrupt 1 priority level
Timer 0 interrupt priority level
External interrupt 0 priority level
SU00763
PT0
PX1
PT1
PS0
PS1
PAD
–
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IP0 (B8H)
Figure 30. Interrupt Priority Register (IP0)
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