HARDWARE
1-40
7540 Group User
’
s Manual
Serial I/O2 operation
By writing to the serial I/O2 register (address 0031
16
) the serial I/
O2 counter is set to
“
7
”
.
After writing, the S
DATA2
pin outputs data every time the transfer
clock shifts from
“
H
”
to
“
L
”
. And, as the transfer clock shifts from
“
L
”
to
“
H
”
, the S
DATA2
pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source,
the following operations execute as the transfer clock counts up to
8.
Serial I/O2 counter is cleared to
“
0
”
.
Transfer clock stops at an
“
H
”
level.
Interrupt request bit is set.
Shift completion flag is set.
Also, the S
DATA2
pin is in a high impedance state after the data
transfer is completed (refer to Fig.37).
When the external clock is selected as the transfer clock source,
the interrupt request bit is set as the transfer clock counts up to 8,
but external control of the clock is required since it does not stop.
Notice that the S
DATA2
pin is not in a high impedance state on the
completion of data transfer.
Also, after the receive operation is completed, the transmit/receive
shift completion flag is cleared by reading the serial I/O2 register.
At transmit, the transmit/receive shift completion flag is cleared
and the transmit operation is started by writing to serial I/O2 regis-
ter.
Fig. 37 Serial I/O2 timing (LSB first)
D
0
Note :
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
S
DATA2
at serial I/O2
input receive
S
DATA2
at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
Transmit/receive shift completion flag set
D
1
D
2
D
3
D
4
D
5
D
6
D
7
When the internal clock is selected as the transfer and the direction register of P1
3
/S
DATA2
pin is set to the input mode,
the S
DATA2
pin is in a high impedance state after the data transfer is completed.
FUNCTIONAL DESCRIPTION