![](http://datasheet.mmic.net.cn/230000/7540_datasheet_15567442/7540_217.png)
7540 Group User
’
s Manual
2-142
APPLICATION
2.9 Oscillation control
2.9.5 State transition
In the 7540 Group, the operation clock is selected from the following 4 types.
f(X
IN
)/2 (high-speed mode)
f(X
IN
)/8 (middle-speed mode)
Ring oscillator
f(X
IN
) (double-speed mode) (
Note 1
)
Note 1:
f(X
IN
) can be used only at the ceramic oscillation. Do not use f(X
IN
) at RC oscillation.
Also, in the 7540 Group, the function to stop CPU operation by software and to keep CPU wait in the
following 2-type low power dissipation.
G
Stop mode with the
STP
instruction (
Notes 2, 3, 4, 5, 6, 7
)
G
Wait mode with the
WIT
instruction (
Note 8
)
Notes 2:
When the stop mode is used, set the oscillation stop detection function to
“
invalid
”
.
3:
When the stop mode is used, set
“
0
”
(
STP
instruction enabled) the
STP
instruction disable bit
of the watchdog timer control register.
4:
Timer 1 can be used to set the oscillation stabilizing time after release of the
STP
instruction. The
oscillation stabilizing time after release of
STP
instruction can be selected from
“
set automatically
”
/
“
not set automatically
”
by the oscillation stabilizing time set bit after release of the
STP
instruction
of MISRG. When
“
0
”
is set to this bit,
“
01
16
”
is set to timer 1 and
“
FF
16
”
is set to prescaler 1
automatically. When
“
1
”
is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set
the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is
used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode.
5:
The
STP
instruction cannot be used during CPU is operating by the ring oscillator.
6:
When the stop mode is used, stop the ring oscillator oscillation.
7:
Do not execute the
STP
instruction during the A-D conversion.
8:
When the wait mode is used, stop the clock except the operation clock source.
Figure 2.9.9 shows the state transition.
Fig. 2.9.9 State transition
S
t
o
p
m
o
d
e
Wait mode
WIT
instruction
O
s
c
i
l
l
a
t
i
o
n
s
t
o
p
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
v
a
l
i
d
CPUM
4
←
1
2
MISRG
1
←
1
2
I
n
t
e
r
r
u
p
t
I
n
t
e
r
r
u
p
t
S
i
n
T
s
P
t
r
u
c
t
i
o
n
WIT
instruction
Interrupt
M
I
S
R
G
1
←
0
2
CPUM
3
←
1
2
CPUM
3
←
0
2
C
P
U
M
7
6
←
1
0
2
C
a
b
P
U
M
7
6
←
0
0
2
1
2
1
2
2
0
1
e
(
N
o
t
)
CPUM
4
←
0
2
MISRG
1
←
1
2
M
I
S
R
G
1
←
0
2
R
e
s
e
t
r
e
l
e
a
s
e
d
S
n
o
c
c
i
t
c
e
l
l
l
a
a
l
a
t
t
e
c
)
i
o
o
r
k
1
O
f
(X
I
f
(X
I
R
i
p
e
N
)
N
)
n
g
r
a
o
t
(
o
s
i
N
s
o
t
i
l
o
1
t
s
o
u
r
c
e
:
n
s
t
e
o
n
p
a
b
l
e
d
S
n
o
c
c
i
t
t
e
i
l
l
l
l
a
a
c
t
o
1
a
t
o
e
c
)
i
o
r
k
2
O
f
(X
I
f
(X
I
R
i
p
e
N
)
N
)
n
g
r
a
o
t
(
o
s
i
N
s
o
l
s
o
u
r
c
e
:
t
n
e
n
e
n
a
b
e
l
d
e
d
l
S
n
i
l
c
c
i
t
c
a
l
l
l
a
a
l
t
a
t
t
e
c
r
i
o
o
r
k
(
n
e
3
N
n
s
O
R
f
(
R
p
i
n
X
I
i
n
e
g
N
)
g
r
a
o
o
t
s
o
s
i
o
c
s
l
i
l
o
o
t
o
o
e
a
u
t
e
n
a
l
b
r
c
3
b
e
e
)
l
e
d
:
d
S
n
i
l
c
c
i
t
c
a
l
l
l
a
a
l
t
a
t
t
o
o
t
o
e
c
r
i
o
r
k
(
n
e
4
s
O
R
f
(X
I
R
i
p
i
n
e
g
N
)
n
g
r
a
o
o
o
t
s
i
o
c
s
s
l
i
l
N
n
o
o
s
a
u
t
e
o
l
b
r
c
3
p
e
e
)
:
t
d
N
(
1
o
)
t
s
G
G
G
)
E
s
3
)
e
I
n
e
s
l
f
f
f
x
a
n
s
W
i
s
a
o
e
(
X
I
(
X
I
(
X
I
e
t
e
o
p
e
h
p
c
c
C
N
C
D
H
M
o
p
c
n
e
t
e
N
)
N
)
N
)
c
u
3
p
e
e
d
e
n
e
r
o
r
P
U
O
P
U
o
u
i
g
i
d
s
r
d
/
/
t
e
’
r
a
m
t
h
f
o
d
i
M
P
M
b
h
-
d
l
w
a
2
8
(
i
i
o
(
(
d
t
o
t
i
t
o
r
c
n
h
m
o
h
e
s
o
o
d
e
r
m
n
g
7
6
i
n
s
4
l
e
-
s
p
e
-
s
h
t
i
g
i
u
t
a
n
e
s
t
e
d
t
o
→
t
r
u
→
s
p
e
e
p
e
c
h
o
l
e
h
d
b
s
t
c
a
t
,
t
f
o
-
d
l
e
t
a
e
l
o
i
s
e
e
h
1
c
t
1
2
e
e
d
e
c
c
C
s
l
e
-
s
t
2
c
s
t
x
e
0
2
i
o
n
(
d
m
o
d
m
l
o
P
p
-
p
e
’
k
e
r
a
e
d
c
s
U
e
s
p
e
t
r
a
s
l
e
n
c
i
(
k
o
e
t
f
k
u
c
d
e
e
a
n
f
t
e
o
c
s
u
t
v
i
S
r
l
m
e
d
d
s
r
u
r
t
e
i
t
i
e
s
i
o
t
a
c
o
e
c
o
m
i
t
s
c
e
d
o
n
t
h
n
t
e
=
d
d
m
o
d
i
o
t
a
=
f
o
s
e
r
2
f
i
)
d
e
s
i
l
r
r
t
a
N
a
t
→
(X
I
v
i
N
)
i
o
,
t
r
h
a
e
t
i
f
o
.
l
l
o
w
i
n
g
c
a
n
b
e
k
s
n
o
e
o
e
,
t
i
z
i
n
t
h
t
O
i
o
)
o
a
i
g
e
e
P
o
s
n
t
n
l
y
o
C
2
→
i
n
f
C
t
a
t
3
X
I
s
P
a
t
t
N
c
i
U
o
a
o
l
a
c
s
t
r
u
P
U
e
3
s
c
t
s
t
o
l
o
a
t
c
t
c
e
a
c
r
c
e
i
o
l
o
r
t
i
l
,
k
3
n
c
a
e
l
t
m
2
a
t
h
d
→
a
s
k
.
i
o
o
e
i
v
c
r
o
.
s
c
i
l
l
a
t
i
o
n
)
(
2
n
b
e
g
t
t
i
n
m
i
s
s
s
d
o
a
h
o
(
I
l
i
d
n
t
e
w
l
r
n
e
a
4
-
i
t
t
b
i
o
.
(
4
)
s
t
e
l
o
w
)
S
m
d
t
a
o
e
o
t
d
a
d
e
e
3
a
t
r
e
→
t
r
i
n
g
a
t
s
t
a
s
o
t
e
s
i
l
s
c
l
a
c
4
i
)
l
t
l
l
i
n
o
n
g
o
c
l
o
a
a
r
t
:
o
o
r
:
O
N
N
O
P
O
P
1
3
N
r
:
P
r
i
g
i
t
0
Reset state
CPUM
76
←
10
2
C
P
U
M
7
6
←
0
0
2
1
2
1
2
2
0
1
e
(
N
o
t
)
S
n
o
c
c
i
t
c
t
e
i
l
l
l
l
a
a
l
a
t
t
o
1
t
o
e
c
)
i
o
r
k
2
’
s
O
f
(X
I
f
(X
I
R
i
p
e
N
)
N
)
n
g
r
a
o
t
(
o
s
i
N
s
o
o
u
r
c
e
:
n
e
n
e
n
a
a
b
b
e
l
d
e
d
l
State 3’
Operation clock source:
Ring oscillator (Note 3)
f(X
IN
) oscillation enabled
Ring oscillator enalbed