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7540 Group User
’
s Manual
2-104
APPLICATION
2.6 Serial I/O1
Fig. 2.6.7 Structure of Interrupt request register 1
Fig. 2.6.8 Structure of Interrupt control register 1
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
0
Interrupt request register 1 (IREQ1) [Address : 3C
16
]
Serial I/O1 receive
interrupt request bit
Serial I/O1 transmit interrupt
request bit
INT
0
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
:
These bits can be cleared to
“
0
”
by program, but cannot be set to
“
1
”
.
INT
1
interrupt request bit
Key-on wake up interrupt
request bit
Timer X interrupt request bit
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Serial I/O1 receive
interrupt enable bit
Serial I/O1 transmit interrupt
enable bit
INT
0
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
INT
1
interrupt enable bit
Key-on wake up interrupt
enable bit
Timer X interrupt enable bit