參數(shù)資料
型號(hào): 6PAIC3106IRGZRQ1
廠商: Texas Instruments
文件頁(yè)數(shù): 78/103頁(yè)
文件大?。?/td> 0K
描述: IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 102(差分),92 / 95(單端)
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 91 / 99(差分),91 / 92(單端)
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-VQFN 裸露焊盤(pán)(7x7)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1077 (CN2011-ZH PDF)
其它名稱: 296-25253-6
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Table 96. Page 0 / Register 87: LINE2L to RIGHT_LOP/M Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to RIGHT_LOP/M
1: LINE2L is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
LINE2L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
Table 97. Page 0 / Register 88: PGA_L to RIGHT_LOP/M Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to RIGHT_LOP/M
1: PGA_L is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
PGA_L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
Table 98. Page 0 / Register 89: DAC_L1 to RIGHT_LOP/M Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP/M
1: DAC_L1 is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
DAC_L1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
Table 99. Page 0 / Register 90: LINE2R to RIGHT_LOP/M Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to RIGHT_LOP/M
1: LINE2R is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
LINE2R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
Table 100. Page 0 / Register 91: PGA_R to RIGHT_LOP/M Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to RIGHT_LOP/M
1: PGA_R is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
PGA_R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
Table 101. Page 0 / Register 92: DAC_R1 to RIGHT_LOP/M Volume Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to RIGHT_LOP/M
1: DAC_R1 is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
DAC_R1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
76
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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