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參數(shù)資料
| 型號： | 6PAIC3106IRGZRQ1 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 15/103頁 |
| 文件大小： | 0K |
| 描述： | IC AUDIO CODEC STEREO 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 102（差分），92 / 95（單端） |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 91 / 99（差分），91 / 92（單端） |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-VQFN 裸露焊盤（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1077 (CN2011-ZH PDF) |
| 其它名稱： | 296-25253-6 |
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RA(6)
RA(5)
RA(0)
Don’tCare
7-bitRegister Address
Read
8-bitRegisterData
SS
SCLK
MOSI
MISO
Hi-Z
D(7)
D(6)
D(0)
Hi-Z
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Figure 15. SPI Read
In the SPI control mode, the TLV320AIC3106 uses the pins MFP0 = SSB, MFP1 = SCLK, MFP2 = MISO, MFP3
= MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0).
The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and
peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock
(driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC3106) depend on
a master to start and synchronize transmissions.
A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the
slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI
pin, a byte shifts out on the MISO pin to the master shift register.
The TLV320AIC3106 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor SPI
control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the
first serial clock edge. The SSB pin can remain low between transmissions; however, the TLV320AIC3106 only
interprets the first 8 bits transmitted after the falling edge of SSB as a command byte, and the next 8 bits as a
data byte only if writing to a register. Reserved register bits should be written to their default values.
SPI COMMUNICATION PROTOCOL
The TLV320AIC3106 is entirely controlled by registers. Reading and writing these registers is accomplished by
the use of an 8-bit command, which is sent to the MOSI pin of the part prior to the data for that register. The
command is constructed as shown in Table X. The first 7 bits specify the register address which is being written
or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of data
flow on the serial bus. In the case of a register write, the R/W bit should be set to 0. A second byte of data is
sent to the MOSI pin and contains the data to be written to the register.
Reading of registers is accomplished in similar fashion. The 8-bit command word sends the 7-bit register
address, followed by R/W bit = 1 to signify a register read is occurring,. The 8-bit register data is then clocked out
of the part on the MISO pin during the second 8 SCLK clocks in the frame.
Table 1. Command Word
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
R/W
The register map of the TLV320AIC3106 actually consists of multiple pages of registers, with each page
containing 128 registers. The register at address zero on each page is used as a page-control register, and
writing to this register determines the active page for the device. All subsequent read/write operations will access
the page that is active at the time, unless a register write is performed to change the active page. Only two
pages of registers are implemented in this product, with the active page defaulting to page 0 upon device reset.
Copyright 2009–2012, Texas Instruments Incorporated
19
Product Folder Links: TLV320AIC3106-Q1
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