參數(shù)資料
型號: 6PAIC3106IRGZRQ1
廠商: Texas Instruments
文件頁數(shù): 25/103頁
文件大?。?/td> 0K
描述: IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 102(差分),92 / 95(單端)
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 91 / 99(差分),91 / 92(單端)
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-VQFN 裸露焊盤(7x7)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1077 (CN2011-ZH PDF)
其它名稱: 296-25253-6
K*R/P
2/Q
GPIO2
PLL_CLKIN
CODEC
CODEC_CLKIN
PLL_OUT
K=J.D
J=1,2,3,…..,62,63
D=0000,0001,….,9998,9999
R=1,2,3,4,….,15,16
P=1,2,….,7,8
Q=2,3,…..,16,17
MCLK
BCLK
CLKDIV_IN
PLL_IN
WCLK =Fsref/ Ndac
GPIO1 =Fsref/ Nadc
ADC_FS
DAC_FS
Ndac=1,1.5,2,…..,5.5,6
DACDRA =>Ndac=0.5
Nadc=1,1.5,2,…..,5.5,6
ADCDRA =>Nadc=0.5
CODEC_CLK=256*Fsref
CLKDIV_OUT
1/8
PLLDIV_OUT
CLKDIV_CLKIN
2/(N*M)
CLKMUX _OUT
GPIO1
M=1,2,4,8
N=2,3,……,16,17
CLKOUT
CLKOUT_IN
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Figure 26. Audio Clock Generation Processing
The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK or
GPIO2 inputs can also be used to generate the internal audio master clock.
This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is not
powered up. The user can supply a separate clock to GPIO2, route this through the PLL, with the resulting output
clock driven out GPIO1, for use by other devices in the system
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus
paid to the standard MCLK rates already widely used.
When the PLL is disabled,
fS(ref) = CLKDIV_IN / (128 × Q)
Where Q = 2, 3, …, 17
CLKDIV_IN can be MCLK, BCLK, or GPIO2, selected by register 102, bits D7-D6.
28
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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