參數(shù)資料
型號: 6PAIC3106IRGZRQ1
廠商: Texas Instruments
文件頁數(shù): 14/103頁
文件大小: 0K
描述: IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 102(差分),92 / 95(單端)
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 91 / 99(差分),91 / 92(單端)
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-VQFN 裸露焊盤(7x7)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1077 (CN2011-ZH PDF)
其它名稱: 296-25253-6
RA(6)
RA(5)
RA(0)
D(7)
D(6)
D(0)
7-bitRegister Address
Write
8-bitRegisterData
SS
SCLK
MOSI
MISO
Hi-Z
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
OVERVIEW
The TLV320AIC3106 is a highly flexible, low power, stereo audio codec with extensive feature integration,
intended for applications in smart phones, PDAs, and portable computing, communication, and entertainment
applications. Available in a 7-mm x 7-mm 48-lead QFN package, the product integrates a host of features to
reduce cost, board space, and power consumption in space-constrained, battery-powered, portable applications.
The TLV320AIC3106 consists of the following blocks:
Stereo audio multi-bit delta-sigma DAC (8 kHz–96 kHz)
Stereo audio multi-bit delta-sigma ADC (8 kHz–96 kHz)
Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, notch filter, de-emphasis)
Six audio inputs
Four high-power audio output drivers (headphone drive capability)
Three fully differential line output drivers
Fully programmable PLL
Headphone/headset jack detection with interrupt
Communication to the TLV320AIC3106 for control is pin-selectable (using the SELECT pin) as either SPI or I2C.
The SPI interface requires that the Slave Select signal (MFP0) be driven low to communicate with the
TLV320AIC3106. Data is then shifted into or out of the TLV320AIC3106 under control of the host
microprocessor, which also provides the serial data clock. The I2C interface supports both standard and fast
communication modes, and also enables cascading of up to four multiple codecs on the same I2C bus through
the use of two pins for addressing (MFP0, MFP1).
HARDWARE RESET
The TLV320AIC3106 requires a hardware reset after power-up for proper operation. After all power supplies are
at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320AIC3106 may not respond properly to register reads/writes.
DIGITAL CONTROL SERIAL INTERFACE
The TLV320AIC3106 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SELECT pin. For SPI, SELECT should be tied high; for I2C, SELECT should be tied low. It is not
recommended to change the state of SELECT during device operation.
SPI CONTROL MODE
Figure 14. SPI Write
18
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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