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參數(shù)資料
| 型號(hào)： | 6PAIC3106IRGZRQ1 |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 33/103頁(yè) |
| 文件大小： | 0K |
| 描述： | IC AUDIO CODEC STEREO 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 102（差分），92 / 95（單端） |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 91 / 99（差分），91 / 92（單端） |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 48-VQFN 裸露焊盤(pán)（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1077 (CN2011-ZH PDF) |
| 其它名稱： | 296-25253-6 |
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Decay Time
Target
Level
Input
Signal
Output
Signal
AGC
Gain
Attack
Time
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Figure 28. Typical Operation of the AGC Algorithm During Speech Recording
Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time
constants are achieved using the fS(ref) value programmed in the control registers. However, if the fS(ref) is set in
the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different
fS(ref) in practice, then the time constants would not be correct.
The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the
clock set up that is used. Table 4 shows the relationship of the NADC ratio to the maximum time available for the
AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit any
practical AGC decay time that is needed by the system.
STEREO AUDIO DAC
The TLV320AIC3106 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each
channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multi-bit
digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced
performance at low sampling rates through increased oversampling and image filtering, thereby keeping
quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the
audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × fS(ref) and
changing the oversampling ratio as the input sample rate is changed. For an fS(ref) of 48 kHz, the digital delta-
sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within
the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for an
fS(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.
The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is
enabled in the DAC.
Allowed Q values = 4, 8, 9, 12, 16
Q values where equivalent fS(ref) can be achieved by turning on PLL
Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16.0 and PLL enabled)
Q = 10, 14 (set P = 5, 7 and K = 8.0 and PLL enabled)
Copyright 2009–2012, Texas Instruments Incorporated
35
Product Folder Links: TLV320AIC3106-Q1
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