參數(shù)資料
型號(hào)： 6PAIC3106IRGZRQ1
廠商： Texas Instruments
文件頁數(shù)： 54/103頁
文件大?。?/td> 0K
描述： IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 102（差分），92 / 95（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 91 / 99（差分），91 / 92（單端）
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-VQFN 裸露焊盤（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1077 (CN2011-ZH PDF)
其它名稱： 296-25253-6
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Table 20. Page 0 / Register 12: Audio Codec Digital Filter Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Left ADC Highpass Filter Control
00: Left ADC highpass filter disabled
01: Left ADC highpass filter –3-dB frequency = 0.0045 × ADC fS
10: Left ADC highpass filter –3-dB frequency = 0.0125 × ADC fS
11: Left ADC highpass filter –3-dB frequency = 0.025 × ADC fS
D5–D4
R/W
00
Right ADC Highpass Filter Control
00: Right ADC highpass filter disabled
01: Right ADC highpass filter –3-dB frequency = 0.0045 × ADC fS
10: Right ADC highpass filter –3-dB frequency = 0.0125 × ADC fS
11: Right ADC highpass filter –3-dB frequency = 0.025 × ADC fS
D3
R/W
0
Left DAC Digital Effects Filter Control
0: Left DAC digital effects filter disabled (bypassed)
1: Left DAC digital effects filter enabled
D2
R/W
0
Left DAC De-emphasis Filter Control
0: Left DAC de-emphasis filter disabled (bypassed)
1: Left DAC de-emphasis filter enabled
D1
R/W
0
Right DAC Digital Effects Filter Control
0: Right DAC digital effects filter disabled (bypassed)
1: Right DAC digital effects filter enabled
D0
R/W
0
Right DAC De-emphasis Filter Control
0: Right DAC de-emphasis filter disabled (bypassed)
1: Right DAC de-emphasis filter enabled
Table 21. Page 0 / Register 13: Headset / Button Press Detection Register A
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Headset Detection Control
0: Headset detection disabled
1: Headset detection enabled
D6–D5
R
00
Headset Type Detection Results
00: No headset detected
01: Headset without microphone detected
10: Ignore (reserved)
11: Headset with microphone detected
D4–D2
R/W
000
Headset Glitch Suppression Debounce Control for Jack Detection
000: Debounce = 16 ms (sampled with 2-ms clock)
001: Debounce = 32 ms (sampled with 4-ms clock)
010: Debounce = 64 ms (sampled with 8-ms clock)
011: Debounce = 128 ms (sampled with 16-ms clock)
100: Debounce = 256 ms (sampled with 32-ms clock)
101: Debounce = 512 ms (sampled with 64-ms clock)
110: Reserved, do not write this bit sequence to these register bits.
111: Reserved, do not write this bit sequence to these register bits.
D1–D0
R/W
00
Headset Glitch Suppression Debounce Control for Button Press
00: Debounce = 0msec
01: Debounce = 8 ms (sampled with 1-ms clock)
10: Debounce = 16 ms (sampled with 2-ms clock)
11: Debounce = 32 ms (sampled with 4-ms clock)
54
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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