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參數(shù)資料
| 型號(hào)： | 6PAIC3106IRGZRQ1 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 21/103頁 |
| 文件大小： | 0K |
| 描述： | IC AUDIO CODEC STEREO 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 102（差分），92 / 95（單端） |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 91 / 99（差分），91 / 92（單端） |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-VQFN 裸露焊盤（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1077 (CN2011-ZH PDF) |
| 其它名稱： | 296-25253-6 |
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BCLK
WCLK
SDIN/
SDOUT
1
0
1
0
1/fs
LSB
MSB
LeftChannel
RightChannel
2
n1
n3
n2
n1
n3
n2
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC
and DAC sampling frequencies.
The bit clock (BCLK or GPIO2) is used to clock in and out the digital audio data across the serial bus. When in
Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock
mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are
generated, so in general the number of bit clocks per frame will be two times the data width. For example, if data
width is chosen as 16 bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode
will be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be
used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32 × fS or 64 × fS.
In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame will not all be
of equal period, due to the device not having a clean 40 × fS or 48 × fS clock signal readily available. The
average frequency of the bit clock signal is still accurate in these cases (being 40 × fS or 48 × fS), but the
resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC3106 further includes programmability to 3-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to
use a single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface will be put into a 3-state output condition.
RIGHT-JUSTIFIED MODE
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 21. Right-Justified Serial Bus Mode Operation
24
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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