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參數(shù)資料
| 型號(hào)： | 6PAIC3106IRGZRQ1 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 17/103頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC STEREO 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 102（差分），92 / 95（單端） |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 91 / 99（差分），91 / 92（單端） |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-VQFN 裸露焊盤（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1077 (CN2011-ZH PDF) |
| 其它名稱： | 296-25253-6 |
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SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for
addresses 1 to 127 will access registers in page 0. If registers on page 1 must be accessed, the user must write
the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page 1.
After this write, it is recommended the user also read back the page control register, to safely ensure the change
in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now access
registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to
register 0, the page control register, to change the active page back to page 0. After a recommended read of the
page control register, all further read/write operations to addresses 1 to 127 will now access page 0 registers
again.
Limitation on Register Writing
When writing registers in SPI mode related to the audio output drivers mux, mix, gain configuration, etc., do not
use the auto-increment mode. In addition, between two successive writes to these registers, the host should
keep MFP0 (SPI chip select) high for at least 6.25us, to ensure that the register writes have occurred properly.
CONTINUOUS READ / WRITE OPERATION
The TLV320AIC3106 includes the ability to read/write registers continuously, without needing to provide an
address for every register accessed. In SPI mode, a continuous write is executed by transitioning MFP0 (SPI
chip select) low to start the frame, sending the first 8-bit command word to read/write a particular register, and
then sending multiple bytes of register data, intended for the addressed register and those following. A
continuous read is done similarly, with multiple bytes read in from the addressed register and the following
registers on the page. When the MFP0 (SPI chip select) pin is transitioned high again, the frame ends, as does
the continuous read/write operation. A new frame must begin again with a new command word, to start the next
bus transaction.
Note that this continuous read/write operation does not continue past a page boundary. The user should not
attempt to read/write past the end of a page, since this may result in undesirable operation.
I
2C CONTROL MODE
The TLV320AIC3106 supports the I2C control protocol when the SELECT pin is tied low, using 7-bit addressing
and capable of both standard and fast modes. For I2C fast mode, note that the minimum timing for each of tHD-
STA, tSU-STA, and tSU-STO is 0.9 us, as seen in Figure 16. When in I2C control mode, the TLV320AIC3106
can be configured for one of four different addresses, using the multifunction pins MFP0 and MFP1, which
control the two LSBs of the device address. The 5 MSBs of the device address are fixed as 00110 and cannot be
changed, while the two LSBs are given by MFP1:MFP0. This results in four possible device addresses:
Table 2. I2C Slave Device Addresses for MFP1, MFP0
Settings
MFP1
MFP0
Device
Address
0
0011000
0
1
0011001
1
0
0011010
1
0011011
20
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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