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參數(shù)資料
| 型號： | 5962R0150201VYC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 9/55頁 |
| 文件大?。?/td> | 685K |
| 代理商： | 5962R0150201VYC |
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17
The UT1750AR loads the eight bits of serial data into the lower
eight bits of the TXMT (figure 13).
The Pending Interrupt Register (PI)
The Pending Interrupt Register (PI) contains information on
pending interrupts attempting to vector the Instruction Counter
Register (IC) to a new location. Software or hardware controls
the PI. Any system interrupt, when active, sets the
corresponding bit in the PI. RISC I/O instructions can also set,
clear, and read the PI (figure 14).
The Fault Register (FT)
The UT1750AR uses the Fault Register (FT) (figure 15) to
indicate the occurrence of a machine-error fault. A machine-
error fault cannot be disabled. The UT1750AR uses the logical
OR combination of the 16 FT bits to generate the Machine Error
interrupt, bit 14 of the PI. Any bits in the FT the UT1750AR
does not use are set to a logic zero. The UT1750AR reads, loads,
and clears the FT with RISC I/O instructions. The configuration
of the FT is shown in figure 15.
Bit Definitions
All bits in the Fault Register are active when high.
BIT
NUMBER
MNEMONIC
DESCRIPTION
15
CMPF
CPU Memory Protect Fault.
This bit indicates the
UT1750AR has detected an
access fault, write-protect
fault, or an execute-protect
fault. [0]
14
DMPF
DMA Memory Protect Fault.
This bit indicates a DMA
device has detected an access
fault or a write-protect fault.
[0]
13
MPF
Memory Parity Fault. [0]
12
PCPF
Parallel I/O (PIO) Channel
Parity Fault. [0] No user
access.
11
DCPF
DMA Channel Parity Fault.
[0] No user access.
10
ICF
Illegal Command Fault. This
bit indicates an attempt to
execute an unimplemented or
reserved I/O command. [0]
9
PTF
PIO Transmission Fault. Can
wire-OR I/O error-checking
devices together and feed
them
into this input to indicate an
error. [0] No user access.
8
SYSFLT
System Fault. [0]
7
IAF
Illegal Address Fault. This bit
indicates addressing a memory
location not physically
present. [0]
6
IIF
Illegal Instruction Fault. This
bit indicates an attempt to
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
D
C
0
D
C
5
D
C
4
D
C
3
D
C
2
D
C
1
D
C
D
C
6
T
X
D
T
X
D
T
X
D
T
X
D
T
X
D
T
X
D
T
X
D
T
X
D
MSB
LSB
Figure 13. The UART Transmitter
6
7
DC = Don’t Care
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
P
W
D
N
M
C
H
E
I
N
T
O
F
L
P
O
F
I
P
O
E
X
C
L
F
L
P
T
I
M
6
T
I
M
I
N
T
I
N
T
I
N
T
I
O
L
I
N
T
I
O
L
I
N
T
MSB
LSB
Figure 14. The Pending Interrupt Register (PI)
U
A
1 B
2
3
1
4
2
5
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
MEM
PARITY
I/O
S
Y
F
6
ILLEGAL
T
R
E
S
BUILT-
MSB
LSB
Figure 15. The Fault Register (FT)
PROT
INSTRUC-
TION AND
ADD FAULT
IN-
TEST
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