參數(shù)資料
型號(hào)： 5962R0150201VYC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144
封裝： CERAMIC, PGA-144
文件頁(yè)數(shù)： 55/55頁(yè)
文件大?。?/td> 685K
代理商： 5962R0150201VYC
9
A0
84
A14
TTO
OPERAND BUSSES
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
Address Bus - Operand. When asserted, this bus is
unidirectional and represents the Operand Address. The bus
is in the high-impedance state when the UT1750AR does
not control the bus. A15 is the most significant bit. The
Operand Address enters a high-impedance state when the
UT1750AR is in the test mode (TEST = 0).
D0
64
H15
TTB
Data Bus - Operand. This bidirectional data bus remains
in a high-impedance state when the UT1750AR does not
control the bus. D15 is the most significant bit. The
Operand Data Bus enters a high-impedance state when
the UT1750AR is in the test mode (TEST = 0).
--
RA0
18
R2
TTO
RISC (Instruction) Address Bus. This unidirectional bus
represents the address of the data in RISC memory. With the
MIL-STD-1750A mode of operation selected (M1750 = 1),
the data from RISC memory is from the emulation ROMs. This
data is the RISC instructions that the UT1750AR executes to
emulate MIL-STD-1750A instructions. RA15 is the most
significant bit. The RISC address enters a high-impedance
state when the UT1750AR is in the test mode (TEST = 0).
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
85
86
87
88
89
90
91
92
93
94
95
96
97
102
103
B12
C11
A13
B11
A12
C10
B10
B9
C9
A10
A9
B8
A8
A7
A6
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
G15
F15
G14
F14
F13
E15
D15
C15
D14
E13
C14
B15
D13
C13
B14
--
RISC BUSSES
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA10
RA11
RA12
RA13
RA14
RA15
19
20
21
22
23
24
25
26
27
28
29
30
31
36
37
P4
N5
R3
P5
R4
N6
P6
P7
N7
R6
R7
P8
R8
R9
R10
--
Continued on page 10.
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